电荷阱闪存位元在180nm CMOS逻辑晶圆厂的演示

S. Sadana, M. Gupta, R. Shankar, S. Singla, H. S. Jatana, U. Ganguly
{"title":"电荷阱闪存位元在180nm CMOS逻辑晶圆厂的演示","authors":"S. Sadana, M. Gupta, R. Shankar, S. Singla, H. S. Jatana, U. Ganguly","doi":"10.1109/icee44586.2018.8937900","DOIUrl":null,"url":null,"abstract":"Embedded non-volatile memory demand has increased manifolds in the recent time because it offers increased functionality and security for the systems. Microcontrollers, secure microprocessor need both advanced logic and NVM on the same die. Flash memory is the most mature memory used as Multi-Time Programmable Non-Volatile Memory (NVM). Traditionally Floating gate flash memory is the most commonly used flash technology where the charge is stored on the conducting floating gate. Floating gate memory is difficult to integrate in the logic process due to complex process integration and need 8-9 extra masks in the logic process to integrate flash technology. In this paper, we demonstrate Si3 N44 Charge Trap Flash (CTF) technology in 180nm CMOS fab. CTF is relatively easy to integrate and require few masks. The initial results show millisecond Program/Erase(P/E) speed, memory window of more than 1V after 1000 cycles and excellent retention with no bit flip after $250^{\\circ}\\mathrm{C}$ bake for 6 hours.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"59 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Demonstration of Charge Trap Flash Bit-Cell in 180nm CMOS Logic Foundry\",\"authors\":\"S. Sadana, M. Gupta, R. Shankar, S. Singla, H. S. Jatana, U. Ganguly\",\"doi\":\"10.1109/icee44586.2018.8937900\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Embedded non-volatile memory demand has increased manifolds in the recent time because it offers increased functionality and security for the systems. Microcontrollers, secure microprocessor need both advanced logic and NVM on the same die. Flash memory is the most mature memory used as Multi-Time Programmable Non-Volatile Memory (NVM). Traditionally Floating gate flash memory is the most commonly used flash technology where the charge is stored on the conducting floating gate. Floating gate memory is difficult to integrate in the logic process due to complex process integration and need 8-9 extra masks in the logic process to integrate flash technology. In this paper, we demonstrate Si3 N44 Charge Trap Flash (CTF) technology in 180nm CMOS fab. CTF is relatively easy to integrate and require few masks. The initial results show millisecond Program/Erase(P/E) speed, memory window of more than 1V after 1000 cycles and excellent retention with no bit flip after $250^{\\\\circ}\\\\mathrm{C}$ bake for 6 hours.\",\"PeriodicalId\":6590,\"journal\":{\"name\":\"2018 4th IEEE International Conference on Emerging Electronics (ICEE)\",\"volume\":\"59 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 4th IEEE International Conference on Emerging Electronics (ICEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/icee44586.2018.8937900\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icee44586.2018.8937900","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

嵌入式非易失性存储器的需求在最近增加了,因为它为系统提供了更多的功能和安全性。微控制器,安全微处理器需要先进的逻辑和NVM在同一个芯片上。闪存是目前最成熟的多时间可编程非易失性存储器(NVM)。传统的浮栅闪存是最常用的闪存技术,其电荷存储在导电浮栅上。浮门存储器由于过程集成复杂,在逻辑过程中难以集成,需要在逻辑过程中额外增加8-9个掩模来集成闪存技术。在本文中,我们在180nm CMOS晶圆厂中演示了si3n44电荷阱闪蒸(CTF)技术。CTF相对容易集成,并且需要很少的掩模。初步结果表明,程序/擦除(P/E)速度为毫秒级,在1000个周期后内存窗口大于1V,并且在$250^{\circ}\ maththrm {C}$烘烤6小时后保持良好,无位翻转。
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Demonstration of Charge Trap Flash Bit-Cell in 180nm CMOS Logic Foundry
Embedded non-volatile memory demand has increased manifolds in the recent time because it offers increased functionality and security for the systems. Microcontrollers, secure microprocessor need both advanced logic and NVM on the same die. Flash memory is the most mature memory used as Multi-Time Programmable Non-Volatile Memory (NVM). Traditionally Floating gate flash memory is the most commonly used flash technology where the charge is stored on the conducting floating gate. Floating gate memory is difficult to integrate in the logic process due to complex process integration and need 8-9 extra masks in the logic process to integrate flash technology. In this paper, we demonstrate Si3 N44 Charge Trap Flash (CTF) technology in 180nm CMOS fab. CTF is relatively easy to integrate and require few masks. The initial results show millisecond Program/Erase(P/E) speed, memory window of more than 1V after 1000 cycles and excellent retention with no bit flip after $250^{\circ}\mathrm{C}$ bake for 6 hours.
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