H. Ho, M. Steigerwalt, B. Walsh, T.L. Doney, D. Wildrick, P. McFarland, J. Benedict, K. Bard, D. Pendleton, J.D. Lee, S. Maurer, B. Corrow, D. Sadana
{"title":"一种0.13 /spl mu/m高性能SOI逻辑技术,内置DRAM,用于片上系统应用","authors":"H. Ho, M. Steigerwalt, B. Walsh, T.L. Doney, D. Wildrick, P. McFarland, J. Benedict, K. Bard, D. Pendleton, J.D. Lee, S. Maurer, B. Corrow, D. Sadana","doi":"10.1109/IEDM.2001.979555","DOIUrl":null,"url":null,"abstract":"Reports the successful implementation of a 0.13 /spl mu/m high-performance, silicon-on-insulator (SOI) logic technology to produce a 0.13 /spl mu/m logic-based embedded DRAM (eDRAM) on substrates composed of both bulk Si and SOI or pattern SOI. eDRAM macros are constructed in bulk regions of the wafer and high-performance logic circuits lie on SOI. Pattern SOI wafers are produced by blocking out selected regions of p-type Si wafers from the separation by implantation of oxygen (SIMOX) implant using a thick (> 1 /spl mu/m) hard mask. Test results indicate that SOI eDRAM yield and retention characteristics are comparable to bulk eDRAM. Based on ring oscillator tests, the use of 0.13 /spl mu/m SOI logic devices improves switching speeds by >20% over 0.13 /spl mu/m bulk technology at 1.2 Vdd. These results pave the way for future generations of low power SOI system-on-a-chip (SOC) applications, starting at the 0.1 /spl mu/m node.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"27 1","pages":"22.3.1-22.3.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A 0.13 /spl mu/m high-performance SOI logic technology with embedded DRAM for system-on-a-chip application\",\"authors\":\"H. Ho, M. Steigerwalt, B. Walsh, T.L. Doney, D. Wildrick, P. McFarland, J. Benedict, K. Bard, D. Pendleton, J.D. Lee, S. Maurer, B. Corrow, D. Sadana\",\"doi\":\"10.1109/IEDM.2001.979555\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Reports the successful implementation of a 0.13 /spl mu/m high-performance, silicon-on-insulator (SOI) logic technology to produce a 0.13 /spl mu/m logic-based embedded DRAM (eDRAM) on substrates composed of both bulk Si and SOI or pattern SOI. eDRAM macros are constructed in bulk regions of the wafer and high-performance logic circuits lie on SOI. Pattern SOI wafers are produced by blocking out selected regions of p-type Si wafers from the separation by implantation of oxygen (SIMOX) implant using a thick (> 1 /spl mu/m) hard mask. Test results indicate that SOI eDRAM yield and retention characteristics are comparable to bulk eDRAM. Based on ring oscillator tests, the use of 0.13 /spl mu/m SOI logic devices improves switching speeds by >20% over 0.13 /spl mu/m bulk technology at 1.2 Vdd. These results pave the way for future generations of low power SOI system-on-a-chip (SOC) applications, starting at the 0.1 /spl mu/m node.\",\"PeriodicalId\":13825,\"journal\":{\"name\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"volume\":\"27 1\",\"pages\":\"22.3.1-22.3.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2001.979555\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979555","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.13 /spl mu/m high-performance SOI logic technology with embedded DRAM for system-on-a-chip application
Reports the successful implementation of a 0.13 /spl mu/m high-performance, silicon-on-insulator (SOI) logic technology to produce a 0.13 /spl mu/m logic-based embedded DRAM (eDRAM) on substrates composed of both bulk Si and SOI or pattern SOI. eDRAM macros are constructed in bulk regions of the wafer and high-performance logic circuits lie on SOI. Pattern SOI wafers are produced by blocking out selected regions of p-type Si wafers from the separation by implantation of oxygen (SIMOX) implant using a thick (> 1 /spl mu/m) hard mask. Test results indicate that SOI eDRAM yield and retention characteristics are comparable to bulk eDRAM. Based on ring oscillator tests, the use of 0.13 /spl mu/m SOI logic devices improves switching speeds by >20% over 0.13 /spl mu/m bulk technology at 1.2 Vdd. These results pave the way for future generations of low power SOI system-on-a-chip (SOC) applications, starting at the 0.1 /spl mu/m node.