{"title":"0.13um硅化CMOS技术中esd保护n-MOSFET的布局优化和建模","authors":"Jia Yuxi, Li Jiao, Ran Feng, Dian Yang","doi":"10.1109/ICEPT.2008.4607003","DOIUrl":null,"url":null,"abstract":"In this paper, a lot of CMOS devices with different device dimensions, spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection in 0.13 um Silicide CMOS Technology. The dependences of layout parameters on ESD protection ability of GGNMOS are investigated by using the TLP (transmission line pulsing) measurement technique. A DC model for modeling ESD NMOS snapback characteristics is also presented in this paper.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"39 1","pages":"1-6"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Layout optimization and modeling of an ESD-protection n-MOSFET in 0.13um silicide CMOS technology\",\"authors\":\"Jia Yuxi, Li Jiao, Ran Feng, Dian Yang\",\"doi\":\"10.1109/ICEPT.2008.4607003\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a lot of CMOS devices with different device dimensions, spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection in 0.13 um Silicide CMOS Technology. The dependences of layout parameters on ESD protection ability of GGNMOS are investigated by using the TLP (transmission line pulsing) measurement technique. A DC model for modeling ESD NMOS snapback characteristics is also presented in this paper.\",\"PeriodicalId\":6324,\"journal\":{\"name\":\"2008 International Conference on Electronic Packaging Technology & High Density Packaging\",\"volume\":\"39 1\",\"pages\":\"1-6\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International Conference on Electronic Packaging Technology & High Density Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEPT.2008.4607003\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEPT.2008.4607003","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Layout optimization and modeling of an ESD-protection n-MOSFET in 0.13um silicide CMOS technology
In this paper, a lot of CMOS devices with different device dimensions, spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection in 0.13 um Silicide CMOS Technology. The dependences of layout parameters on ESD protection ability of GGNMOS are investigated by using the TLP (transmission line pulsing) measurement technique. A DC model for modeling ESD NMOS snapback characteristics is also presented in this paper.
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