Q. Luc, C. Fan-Chiang, S. Huynh, P. Huang, H. Do, M. Ha, Y. D. Jin, T. Nguyen, K. Y. Zhang, H. C. Wang, Y. K. Lin, Y. Lin, C. Hu, H. Iwai, E. Chang
{"title":"Hf0.5Zr0.5O2铁电栅极堆负电容InGaAs mosfet的首次实验演示","authors":"Q. Luc, C. Fan-Chiang, S. Huynh, P. Huang, H. Do, M. Ha, Y. D. Jin, T. Nguyen, K. Y. Zhang, H. C. Wang, Y. K. Lin, Y. Lin, C. Hu, H. Iwai, E. Chang","doi":"10.1109/VLSIT.2018.8510644","DOIUrl":null,"url":null,"abstract":"We demonstrate, for the first time, the negative capacitance (NC) In<inf>0.53</inf>Ga<inf>0.47</inf>As nMOSFET with 8-nm Hf<inf>0.5</inf>Zr<inf>0.5</inf>O<inf>2</inf> (HZO) as ferroelectric (FE) dielectric for sub-60 mV/dec subthreshold swing (SS). The impact of annealing treatments on the FE properties and electrical characteristics of NC InGaAs nMOSFETs are investigated. Optimized annealing condition results in NC effects at the HZO/Al<inf>2</inf>O<inf>3</inf>/InGaAs nMOSFETs with steep SS property (~ 11 mV/dec).","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"47-48"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"First Experimental Demonstration of Negative Capacitance InGaAs MOSFETs With Hf0.5Zr0.5O2 Ferroelectric Gate Stack\",\"authors\":\"Q. Luc, C. Fan-Chiang, S. Huynh, P. Huang, H. Do, M. Ha, Y. D. Jin, T. Nguyen, K. Y. Zhang, H. C. Wang, Y. K. Lin, Y. Lin, C. Hu, H. Iwai, E. Chang\",\"doi\":\"10.1109/VLSIT.2018.8510644\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate, for the first time, the negative capacitance (NC) In<inf>0.53</inf>Ga<inf>0.47</inf>As nMOSFET with 8-nm Hf<inf>0.5</inf>Zr<inf>0.5</inf>O<inf>2</inf> (HZO) as ferroelectric (FE) dielectric for sub-60 mV/dec subthreshold swing (SS). The impact of annealing treatments on the FE properties and electrical characteristics of NC InGaAs nMOSFETs are investigated. Optimized annealing condition results in NC effects at the HZO/Al<inf>2</inf>O<inf>3</inf>/InGaAs nMOSFETs with steep SS property (~ 11 mV/dec).\",\"PeriodicalId\":6561,\"journal\":{\"name\":\"2018 IEEE Symposium on VLSI Technology\",\"volume\":\"38 1\",\"pages\":\"47-48\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2018.8510644\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510644","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
First Experimental Demonstration of Negative Capacitance InGaAs MOSFETs With Hf0.5Zr0.5O2 Ferroelectric Gate Stack
We demonstrate, for the first time, the negative capacitance (NC) In0.53Ga0.47As nMOSFET with 8-nm Hf0.5Zr0.5O2 (HZO) as ferroelectric (FE) dielectric for sub-60 mV/dec subthreshold swing (SS). The impact of annealing treatments on the FE properties and electrical characteristics of NC InGaAs nMOSFETs are investigated. Optimized annealing condition results in NC effects at the HZO/Al2O3/InGaAs nMOSFETs with steep SS property (~ 11 mV/dec).