Cu Pillar with Nanocopper Caps: The Next Interconnection Node Beyond Traditional Cu Pillar

Off-chip interconnection pitch scaling has been aggressively driven over the last several decades by the continuous need for higher bandwidth and computing power in smaller form factors in emerging high-performance computing systems. It is expected to reach below 10µm I/O pitch in the near future, beyond the fundamental limits of traditional solder-based interconnection technologies. While the Cu pillar with solder caps technology remains attractive in chip-to-substrate (C2S) applications as it can accommodate substrate and chip non-coplanarities during assembly through melting of the solder, all-Cu interconnections are now pursued as the next interconnection node for their pitch and performance scalability. However, direct Cu-Cu bonding faces several key challenges that have hindered large-scale adoption in C2S, including its relatively high elastic modulus, giving low compliance in assembly. To address this challenge, a novel interconnection technology - Cu pillar with nanocopper caps - is proposed where a solid-state sub-20 GPa modulus nanoporous Cu cap is introduced to replace the solder cap and retain solder-like compliance in assembly, while achieving bulk-like properties through densification in low-temperature sintering. This paper presents the design of this new interconnection system, the developed wafer bumping process, compatible with current industry infrastructures, and a first assembly demonstration where a seamless interface was achieved.