用于SDR应用开发的高速采集和存储平台

2011 VII Southern Conference on Programmable Logic (SPL) Pub Date : 2011-04-13 DOI:10.1109/SPL.2011.5782619

Jorge Cogo, Javier G. García, P. A. Roncagliolo, C. Muravchik

{"title":"用于SDR应用开发的高速采集和存储平台","authors":"Jorge Cogo, Javier G. García, P. A. Roncagliolo, C. Muravchik","doi":"10.1109/SPL.2011.5782619","DOIUrl":null,"url":null,"abstract":"In this work we present the design of an FPGA based platform for acquiring and storing signals for SDR applications. The system comprises an embedded RISC processor, an A/D converter, RAM memory chips and a DMA controller core. This last component was designed from scratch to meet the high data rate and bulk requirements.","PeriodicalId":6329,"journal":{"name":"2011 VII Southern Conference on Programmable Logic (SPL)","volume":"79 1","pages":"19-24"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"High speed acquisition and storage platform for SDR applications development\",\"authors\":\"Jorge Cogo, Javier G. García, P. A. Roncagliolo, C. Muravchik\",\"doi\":\"10.1109/SPL.2011.5782619\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work we present the design of an FPGA based platform for acquiring and storing signals for SDR applications. The system comprises an embedded RISC processor, an A/D converter, RAM memory chips and a DMA controller core. This last component was designed from scratch to meet the high data rate and bulk requirements.\",\"PeriodicalId\":6329,\"journal\":{\"name\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"volume\":\"79 1\",\"pages\":\"19-24\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 VII Southern Conference on Programmable Logic (SPL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPL.2011.5782619\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 VII Southern Conference on Programmable Logic (SPL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2011.5782619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

在这项工作中，我们提出了一个基于FPGA的平台的设计，用于SDR应用的信号采集和存储。该系统由嵌入式RISC处理器、A/D转换器、RAM存储芯片和DMA控制器核心组成。最后一个组件是从头开始设计的，以满足高数据速率和批量需求。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

High speed acquisition and storage platform for SDR applications development

In this work we present the design of an FPGA based platform for acquiring and storing signals for SDR applications. The system comprises an embedded RISC processor, an A/D converter, RAM memory chips and a DMA controller core. This last component was designed from scratch to meet the high data rate and bulk requirements.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2011 VII Southern Conference on Programmable Logic (SPL)

自引率

0.00%

发文量

期刊最新文献

Using partial reconfigurability to aid debugging of FPGA designs Architecture driven memory allocation for FPGA based real-time video processing systems Soft error in FPGA-implemented asynchronous circuits Experiences applying framework-based functional verification to a design for programmable logic A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor