Hong Zhou, D. Kwon, A. Sachid, Y. Liao, K. Chatterjee, A. Tan, A. Yadav, C. Hu, S. Salahuddin
{"title":"负电容,n沟道,Si finfet:双向低于60 mV/dec,负DIBL,负差分电阻和改进的短沟道效应","authors":"Hong Zhou, D. Kwon, A. Sachid, Y. Liao, K. Chatterjee, A. Tan, A. Yadav, C. Hu, S. Salahuddin","doi":"10.1109/VLSIT.2018.8510691","DOIUrl":null,"url":null,"abstract":"We report on negative capacitance (NC) FinFETs with ferroelectric Hf0.5Zr0.5O2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (LCH) of 450 nm to 30 nm and multiple fin widths (WFIN) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), <60 mV/decade subthreshold swing (SS) with an average SS of 54.5 mV/dec for ~2 orders of ID and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same Lch/WFin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"19 1","pages":"53-54"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":"{\"title\":\"Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect\",\"authors\":\"Hong Zhou, D. Kwon, A. Sachid, Y. Liao, K. Chatterjee, A. Tan, A. Yadav, C. Hu, S. Salahuddin\",\"doi\":\"10.1109/VLSIT.2018.8510691\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report on negative capacitance (NC) FinFETs with ferroelectric Hf0.5Zr0.5O2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (LCH) of 450 nm to 30 nm and multiple fin widths (WFIN) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), <60 mV/decade subthreshold swing (SS) with an average SS of 54.5 mV/dec for ~2 orders of ID and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same Lch/WFin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.\",\"PeriodicalId\":6561,\"journal\":{\"name\":\"2018 IEEE Symposium on VLSI Technology\",\"volume\":\"19 1\",\"pages\":\"53-54\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"34\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2018.8510691\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510691","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect
We report on negative capacitance (NC) FinFETs with ferroelectric Hf0.5Zr0.5O2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (LCH) of 450 nm to 30 nm and multiple fin widths (WFIN) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), <60 mV/decade subthreshold swing (SS) with an average SS of 54.5 mV/dec for ~2 orders of ID and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same Lch/WFin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.