漏感Si/SiGe CMOS FinFET低功耗应用

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI:10.1109/VLSIT.2018.8510639

G. Tsutsui, C. Durfee, Miaomiao Wang, A. Konar, Heng Wu, S. Mochizuki, R. Bao, S. Bedell, Juntao Li, Huimei Zhou, D. Schmidt, Chun Ju Yang, J. Kelly, Koji Watanabe, T. Levin, W. Kleemeier, D. Guo, D. Sadana, D. Gupta, A. Knorr, H. Bu

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引用次数: 6

摘要

研究了Si/SiGe CMOS FinFET的泄漏。Si帽钝化有效地改善了SiGe pet Dit、亚阈值斜率和迁移率，使pet直流性能提高了20%。SiGe GIDL比Si高9倍，但GIDL限制在50pA/um。SiGe GIDL减少旋钮，以满足Si对应的演示。该结果为Si/SiGe CMOS FinFET的下一阶段打开了大门，例如低功耗和低泄漏应用。

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Leakage aware Si/SiGe CMOS FinFET for low power applications

Leakage in Si/SiGe CMOS FinFET is examined. Si cap passivation effectively improves SiGe pFET Dit, subthreshold slope, and mobility, which improves pFET DC performance by 20%. SiGe GIDL is higher than Si by a factor of 9, though GIDL is limited to 50pA/um. SiGe GIDL reduction knobs to meet Si counterpart are demonstrated. The results open the door to the next stage of Si/SiGe CMOS FinFET such as low power and low leakage applications.

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2018 IEEE Symposium on VLSI Technology

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