K. McStay, D. Chidambarrao, J. Mandelman, J. Beintner, H. Tews, M. Weybright, G. Wang, Y. Li, K. Hummler, R. Divakaruni, W. Bergner, E. Crabbé, G. Bronner, W. Müller
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引用次数: 3
Abstract
The 8F/sup 2/ vertical transistor DRAM cell is a cost-efficient, litho-friendly structure suitable for scaling to sub-100 nm ground rules. In this paper, we report on device design considerations for vertical pass transistors used in ultra-dense DRAM technologies. A double-gate, vertical DRAM pass transistor that meets 1fA off-current requirement and offers twice the current drive of comparable 175 nm planar devices will be presented. Additionally, structural features unique to vertical devices are highlighted.
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