Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015396
A. Kerber, E. Cartier, R. Degraeve, L. Pantisano, P. Roussel, G. Groeseneken
Polarity-dependent charge trapping and defect generation have been observed in SiO/sub 2//Al/sub 2/O/sub 3/ gate stacks with TiN electrodes. For the substrate injection case, electron trapping in the bulk of the Al/sub 2/O/sub 3/ films dominates, whereas hole trap near the Si substrate is observed for gate injection. This asymmetry in defect creation causes an asymmetry in oxide reliability. For gate injection, reliability is limited by the thin SiO/sub 2/ interfacial layer, yielding low beta values, independent of the Al/sub 2/O/sub 3/ thickness. For substrate injection, reliability is limited by electron trap generation in the bulk of the Al/sub 2/O/sub 3/ film, yielding a strong thickness dependence of the beta values, as expected from the percolation model and as observed in SiO/sub 2/ layers of similar thickness.
{"title":"Strong correlation between dielectric reliability and charge trapping in SiO/sub 2//Al/sub 2/O/sub 3/ gate stacks with TiN electrodes","authors":"A. Kerber, E. Cartier, R. Degraeve, L. Pantisano, P. Roussel, G. Groeseneken","doi":"10.1109/VLSIT.2002.1015396","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015396","url":null,"abstract":"Polarity-dependent charge trapping and defect generation have been observed in SiO/sub 2//Al/sub 2/O/sub 3/ gate stacks with TiN electrodes. For the substrate injection case, electron trapping in the bulk of the Al/sub 2/O/sub 3/ films dominates, whereas hole trap near the Si substrate is observed for gate injection. This asymmetry in defect creation causes an asymmetry in oxide reliability. For gate injection, reliability is limited by the thin SiO/sub 2/ interfacial layer, yielding low beta values, independent of the Al/sub 2/O/sub 3/ thickness. For substrate injection, reliability is limited by electron trap generation in the bulk of the Al/sub 2/O/sub 3/ film, yielding a strong thickness dependence of the beta values, as expected from the percolation model and as observed in SiO/sub 2/ layers of similar thickness.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129868390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015421
K. Uejima, T. Yamamoto, T. Mogami
We have developed a design for a polycrystalline (poly-) gate to be used in high performance sub-100 nm CMOS devices. The inversion capacitance (C/sub inv/) in a device with poly-gate was found to obviously decrease as the gate length becomes shorter in the range below 100 nm (C/sub inv/ lowering). The explanation for this C/sub inv/ lowering is as follows: (1) the gate length becoming shorter than the poly-grain size (R/sub G/) and (2) the short dopant-diffusion length from grain boundaries (D/sub H/). Techniques for achieving small values for R/sub G/ and large values for D/sub H/ improved the I/sub D/ figures by +15% for the pFET and by +3% for the nFET that have poly-SiGe gates with L/sub G/=65 nm.
{"title":"Novel polycrystalline gate engineering for high performance sub-100 nm CMOS devices","authors":"K. Uejima, T. Yamamoto, T. Mogami","doi":"10.1109/VLSIT.2002.1015421","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015421","url":null,"abstract":"We have developed a design for a polycrystalline (poly-) gate to be used in high performance sub-100 nm CMOS devices. The inversion capacitance (C/sub inv/) in a device with poly-gate was found to obviously decrease as the gate length becomes shorter in the range below 100 nm (C/sub inv/ lowering). The explanation for this C/sub inv/ lowering is as follows: (1) the gate length becoming shorter than the poly-grain size (R/sub G/) and (2) the short dopant-diffusion length from grain boundaries (D/sub H/). Techniques for achieving small values for R/sub G/ and large values for D/sub H/ improved the I/sub D/ figures by +15% for the pFET and by +3% for the nFET that have poly-SiGe gates with L/sub G/=65 nm.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129011811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015415
D. Kobayashi, T. Shibata, Y. Fujimori, T. Nakamura, H. Takasu
An analog associative memory technology has been developed using ferroelectric materials as a means of storing template vector information. In order to accommodate the associative memory cell to a wide voltage range of the input signal, a hetero-gate floating-gate-MOS structure has been introduced. The concept has been experimentally verified using fabricated test devices and circuits.
{"title":"A ferroelectric analog associative memory technology employing hetero-gate floating-gate-MOS structure","authors":"D. Kobayashi, T. Shibata, Y. Fujimori, T. Nakamura, H. Takasu","doi":"10.1109/VLSIT.2002.1015415","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015415","url":null,"abstract":"An analog associative memory technology has been developed using ferroelectric materials as a means of storing template vector information. In order to accommodate the associative memory cell to a wide voltage range of the input signal, a hetero-gate floating-gate-MOS structure has been introduced. The concept has been experimentally verified using fabricated test devices and circuits.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131922675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015432
T. Ohguro, K. Kojima, H. Momose, S. Nitta, T. Fukuda, T. Enda, Y. Toyoshima
Fully oxygen precipitated (FOP) wafers can suppress slip generation during the STI process and maintain high substrate resistivity. Additional boron implantation can suppress the leakage current between the adjacent wells due to shallow Xj. No effect on MOSFET characteristics by this implantation was observed. The high resistivity substrate (HRS) can provide good ESD performance and suppress the passage of high frequency signals through the substrate in resistors. Thus, HRS with FOP & additional implantation is effective for future mixed signal CMOS with RF circuits.
{"title":"Improvement of high resistivity substrate for future mixed analog-digital applications","authors":"T. Ohguro, K. Kojima, H. Momose, S. Nitta, T. Fukuda, T. Enda, Y. Toyoshima","doi":"10.1109/VLSIT.2002.1015432","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015432","url":null,"abstract":"Fully oxygen precipitated (FOP) wafers can suppress slip generation during the STI process and maintain high substrate resistivity. Additional boron implantation can suppress the leakage current between the adjacent wells due to shallow Xj. No effect on MOSFET characteristics by this implantation was observed. The high resistivity substrate (HRS) can provide good ESD performance and suppress the passage of high frequency signals through the substrate in resistors. Thus, HRS with FOP & additional implantation is effective for future mixed signal CMOS with RF circuits.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133928472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015417
Y. Takao, S. Nakai, Y. Tagawa, S. Otsuka, Y. Sambonsugi, K. Sugiyama, H. Oota, Y. Iriyama, R. Nanjyo, H. Nagai, K. Naitoh, R. Nakamura, S. Sekino, A. Yamanoue, N. Horiguchi, T. Yamamoto, M. Kojima, S. Satoh, T. Sugii, M. Kase, K. Suzuki, M. Nakaishi, M. Miyajima, T. Ohba, I. Hanyu, S. Sugatani
A low-power, high-speed and high-density 100 nm CMOS technology is developed for very-low-voltage (Vds=0.65 V) operation by using ArF 193 nm lithography, high-performance transistors with sidewall notch, high-density SRAM cell (1.16 /spl mu/m/sup 2/) and copper (Cu) and very-low-k (VLK) interconnect (k/sub eff/=3). For reduction of power consumption and improvement of circuit speed in dynamic operation, high-current transistors at low voltage, interconnect with VLK dielectrics and transistors with reduced parasitic capacitance are required. High-performance transistors with sidewall notch to reduce overlap and junction capacitance and Cu/VLK interconnect with low-k SiC barriers realize higher circuit speed by 10% and lower power consumption by 80%, compared to 130 nm CMOS technology.
{"title":"0.65 V device design with high-performance and high-density 100 nm CMOS technology for low operation power application","authors":"Y. Takao, S. Nakai, Y. Tagawa, S. Otsuka, Y. Sambonsugi, K. Sugiyama, H. Oota, Y. Iriyama, R. Nanjyo, H. Nagai, K. Naitoh, R. Nakamura, S. Sekino, A. Yamanoue, N. Horiguchi, T. Yamamoto, M. Kojima, S. Satoh, T. Sugii, M. Kase, K. Suzuki, M. Nakaishi, M. Miyajima, T. Ohba, I. Hanyu, S. Sugatani","doi":"10.1109/VLSIT.2002.1015417","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015417","url":null,"abstract":"A low-power, high-speed and high-density 100 nm CMOS technology is developed for very-low-voltage (Vds=0.65 V) operation by using ArF 193 nm lithography, high-performance transistors with sidewall notch, high-density SRAM cell (1.16 /spl mu/m/sup 2/) and copper (Cu) and very-low-k (VLK) interconnect (k/sub eff/=3). For reduction of power consumption and improvement of circuit speed in dynamic operation, high-current transistors at low voltage, interconnect with VLK dielectrics and transistors with reduced parasitic capacitance are required. High-performance transistors with sidewall notch to reduce overlap and junction capacitance and Cu/VLK interconnect with low-k SiC barriers realize higher circuit speed by 10% and lower power consumption by 80%, compared to 130 nm CMOS technology.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"25 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131805507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015434
T. Ohnakado, A. Furukawa, M. Ono, E. Taniguchi, S. Yamakawa, K. Nishikawa, T. Murakami, Y. Hashizume, K. Sugahara, T. Oomori
A novel depletion-layer-extended transistor (DET) for the RF switch circuit is proposed in a CMOS process, which significantly reduces junction capacitance and increases GND-path resistance in the Si-substrate, with new impurity profiling. This transistor can be simultaneously formed with the conventional transistor with the addition of only one mask-step. By utilizing the DETs, a low 1.4 dB insertion-loss, 5 GHz transmit/receive switch in a 0.18 /spl mu/m CMOS process is realized.
{"title":"A 1.4 dB insertion-loss, 5 GHz transmit/receive switch utilizing novel depletion-layer-extended transistors (DETs) in 0.18 /spl mu/m CMOS process","authors":"T. Ohnakado, A. Furukawa, M. Ono, E. Taniguchi, S. Yamakawa, K. Nishikawa, T. Murakami, Y. Hashizume, K. Sugahara, T. Oomori","doi":"10.1109/VLSIT.2002.1015434","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015434","url":null,"abstract":"A novel depletion-layer-extended transistor (DET) for the RF switch circuit is proposed in a CMOS process, which significantly reduces junction capacitance and increases GND-path resistance in the Si-substrate, with new impurity profiling. This transistor can be simultaneously formed with the conventional transistor with the addition of only one mask-step. By utilizing the DETs, a low 1.4 dB insertion-loss, 5 GHz transmit/receive switch in a 0.18 /spl mu/m CMOS process is realized.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127581502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015401
G. Wilk, M. Green, M. Ho, B. Busch, T. Sorsch, F. Klemens, B. Brijs, R. V. van Dover, A. Kornblit, T. Gustafsson, E. Garfunkel, S. Hillenius, D. Monroe, P. Kalavade, J. Hergenrother
We demonstrate for the first time that chemical oxide underlayers /spl sim/5 /spl Aring/ thick provide improved growth and flatband voltage control of ALD HfO/sub 2/ films compared to thermal oxides. Optimized annealing conditions are shown to greatly reduce both fixed charge and interfacial oxide growth in the high-/spl kappa/ stacks. Extremely small flatband voltage shifts of <30 mV are achieved, corresponding to a very low fixed charge of Q/sub f//spl sim/2E11/cm/sup 2/.
{"title":"Improved film growth and flatband voltage control of ALD HfO/sub 2/ and Hf-Al-O with n/sup +/ poly-Si gates using chemical oxides and optimized post-annealing","authors":"G. Wilk, M. Green, M. Ho, B. Busch, T. Sorsch, F. Klemens, B. Brijs, R. V. van Dover, A. Kornblit, T. Gustafsson, E. Garfunkel, S. Hillenius, D. Monroe, P. Kalavade, J. Hergenrother","doi":"10.1109/VLSIT.2002.1015401","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015401","url":null,"abstract":"We demonstrate for the first time that chemical oxide underlayers /spl sim/5 /spl Aring/ thick provide improved growth and flatband voltage control of ALD HfO/sub 2/ films compared to thermal oxides. Optimized annealing conditions are shown to greatly reduce both fixed charge and interfacial oxide growth in the high-/spl kappa/ stacks. Extremely small flatband voltage shifts of <30 mV are achieved, corresponding to a very low fixed charge of Q/sub f//spl sim/2E11/cm/sup 2/.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115418319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015422
J. Heo, Soo-jin Hong, D. Ahn, Hyun-Duk Cho, M. Park, K. Fujihara, U. Chung, Y. Oh, J. Moon
Highly reliable void free shallow trench isolation (VF-STI) technology by employing polysilazane based inorganic spin-on-glass (P-SOG) is developed for sub-0.1 /spl mu/m devices. In order to overcome the difficulties from the gap-filling and accumulated mechanical stress in STI, a P-SOG pillar is introduced at the trench bottom. As a result, the P-SOG pillar, having low stress, improves data retention time and hot carrier immunity in 256 Mbit DRAM by reducing cumulative STI stress. In addition, VF-STI shows an excellent extendibility in terms of gap filling capability even at an aspect ratio of more than 10 without void formation.
{"title":"Void free and low stress shallow trench isolation technology using P-SOG for sub 0.1 /spl mu/m device","authors":"J. Heo, Soo-jin Hong, D. Ahn, Hyun-Duk Cho, M. Park, K. Fujihara, U. Chung, Y. Oh, J. Moon","doi":"10.1109/VLSIT.2002.1015422","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015422","url":null,"abstract":"Highly reliable void free shallow trench isolation (VF-STI) technology by employing polysilazane based inorganic spin-on-glass (P-SOG) is developed for sub-0.1 /spl mu/m devices. In order to overcome the difficulties from the gap-filling and accumulated mechanical stress in STI, a P-SOG pillar is introduced at the trench bottom. As a result, the P-SOG pillar, having low stress, improves data retention time and hot carrier immunity in 256 Mbit DRAM by reducing cumulative STI stress. In addition, VF-STI shows an excellent extendibility in terms of gap filling capability even at an aspect ratio of more than 10 without void formation.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124145079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015462
W.S. Song, C.S. Lee, K. Park, B. Suh, J.W. Kim, S. Kim, Y. Wee, S. Choi, H. Kang, S. Kim, K. Suh
By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.
{"title":"Re-defining reliability assessment per new intra-via Cu leakage degradation","authors":"W.S. Song, C.S. Lee, K. Park, B. Suh, J.W. Kim, S. Kim, Y. Wee, S. Choi, H. Kang, S. Kim, K. Suh","doi":"10.1109/VLSIT.2002.1015462","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015462","url":null,"abstract":"By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128633648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015426
T. Yamamoto, K. Goto, Y. Tada, Y. Kikuchi, T. Kubo, Y. Wang, S. Talwar, M. Kase, T. Sugii
In this paper, for the first time, we report the characteristics of sub-50 nm pMOSFETs using a laser thermal process (LTP) and the technique for enhancing their drive current. For the process optimization required for the technologies of sub-50 nm MOSFETs, we investigated the issues of LTP and cleared them up. S/D-extension (SDE)-junction depth, overlap and sheet resistance were controlled by pre-amorphization ion implantation (I/I) energies, and the first two parameters could be thus controlled regardless of dopant dose. This enabled us to design highly activated and abrupt box-like dopant profiles without inducing any short channel deterioration. With this technique, we achieved higher drive current pMOSFETs for the same V/sub th/-rolloff and a 13% improvement in drivability for 45 nm pMOSFETs.
{"title":"Drive current enhancement by ideal junction profile using laser thermal process","authors":"T. Yamamoto, K. Goto, Y. Tada, Y. Kikuchi, T. Kubo, Y. Wang, S. Talwar, M. Kase, T. Sugii","doi":"10.1109/VLSIT.2002.1015426","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015426","url":null,"abstract":"In this paper, for the first time, we report the characteristics of sub-50 nm pMOSFETs using a laser thermal process (LTP) and the technique for enhancing their drive current. For the process optimization required for the technologies of sub-50 nm MOSFETs, we investigated the issues of LTP and cleared them up. S/D-extension (SDE)-junction depth, overlap and sheet resistance were controlled by pre-amorphization ion implantation (I/I) energies, and the first two parameters could be thus controlled regardless of dopant dose. This enabled us to design highly activated and abrupt box-like dopant profiles without inducing any short channel deterioration. With this technique, we achieved higher drive current pMOSFETs for the same V/sub th/-rolloff and a 13% improvement in drivability for 45 nm pMOSFETs.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130749040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：