Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

K. Rim, J. Chu, H. Chen, K. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, H.-S.P. Wong
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引用次数: 151

Abstract

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.
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亚100nm应变Si - N-和pmosfet的特性和器件设计
在物理栅极长度低于100 nm的应变si pmosfet中首次证明了电流驱动的增强,以及在L/sub poly/和L/sub eff/低于80 nm和60 nm时具有良好控制阈值电压V/sub T/和重叠电容C/sub OV/特性的nmosfet。在拉伸应变为1.2%(松弛SiGe缓冲液中Ge含量为28%)的应变Si器件中,电子迁移率提高了110%,峰值空穴迁移率提高了45%。
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