An integrated solution with a novel bi-layer etch stop to eliminate 90 nm Cu/low k package fail

Abstract

As the interconnect RC delay becomes a dominant factor in determining the overall circuit performance, the advantages of copper and low k dielectrics become obvious. The integration of copper interconnects and low k dielectrics generates new failure modes and reliability issues. Once the numerous chip-level copper/low k integration problems are worked through, the greatest challenges lie in obtaining production-worthy, high yielding devices that can be packaged and pass standard reliability tests. This work investigates different integrated solutions to solve a packaging problem we encountered. By carefully managing stress, optimizing film stack and packaging condition, an integrated solution has been found and implemented with good yield, manufacturability, reliability and packaging performance.