Pub Date : 2005-12-01DOI: 10.1109/IRWS.2005.1609570
S. Krishnan, M. Quevedo-López, R. Choi, P. Kirsch, C. Young, R. Harris, J. Peterson, Hong-jyh Li, B. Lee, J.C. Lee
Positive bias temperature instability (PBTI) is investigated in ultra-thin high-k films as a function of dielectric thickness on two different interfaces: SiO/sub 2/ and SiON. It is shown that charge trapping-induced threshold voltage (V/sub TH/) instability is exponentially dependent on dielectric thickness (or equivalent oxide thickness [EOT]) in the thickness range investigated. We propose that the significantly reduced charge trapping at thicknesses less than 2.0 nm is due to a change in the physical structure from suppressed crystallization at lesser thicknesses, resulting in reduced trap density. It is also observed that the SiON interface shows higher V/sub TH/ instability than the corresponding SiO/sub 2/ interface, while thickness dependence is the same for both.
{"title":"Charge trapping dependence on the physical structure of ultra-thin ALD-HfSiON/TiN gate stacks","authors":"S. Krishnan, M. Quevedo-López, R. Choi, P. Kirsch, C. Young, R. Harris, J. Peterson, Hong-jyh Li, B. Lee, J.C. Lee","doi":"10.1109/IRWS.2005.1609570","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609570","url":null,"abstract":"Positive bias temperature instability (PBTI) is investigated in ultra-thin high-k films as a function of dielectric thickness on two different interfaces: SiO/sub 2/ and SiON. It is shown that charge trapping-induced threshold voltage (V/sub TH/) instability is exponentially dependent on dielectric thickness (or equivalent oxide thickness [EOT]) in the thickness range investigated. We propose that the significantly reduced charge trapping at thicknesses less than 2.0 nm is due to a change in the physical structure from suppressed crystallization at lesser thicknesses, resulting in reduced trap density. It is also observed that the SiON interface shows higher V/sub TH/ instability than the corresponding SiO/sub 2/ interface, while thickness dependence is the same for both.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115066654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609593
C. Parthasarathy, M. Denais, V. Huard, G. Ribes, E. Vincent, A. Bravaix
This paper discusses the characterization and modeling methodology for NBTI for subsequent use in reliability simulations. Given the integral recovery post NBTI stress, we use on-the-fly technique to measure degradation. A new and fully experimental means of interpretation of results from OTF is presented. We also present some new evidence of hole-trapping/detrapping during NBTI degradation
{"title":"Characterization and modeling NBTI for design-in reliability","authors":"C. Parthasarathy, M. Denais, V. Huard, G. Ribes, E. Vincent, A. Bravaix","doi":"10.1109/IRWS.2005.1609593","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609593","url":null,"abstract":"This paper discusses the characterization and modeling methodology for NBTI for subsequent use in reliability simulations. Given the integral recovery post NBTI stress, we use on-the-fly technique to measure degradation. A new and fully experimental means of interpretation of results from OTF is presented. We also present some new evidence of hole-trapping/detrapping during NBTI degradation","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115148230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609568
C. Young, D. Heh, S. Nadkarni, R. Choi, J. Peterson, H. Harris, J. Sim, S. Krishnan, J. Barnett, E. Vogel, B. Lee, P. Zeitzoff, G.A. Brown, G. Bersuker
Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2 /HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate stacks occurs primarily within the interfacial SiO2 layer (IL) on the as-grown "precursor" defects most likely caused by the overlaying HfO2 layer. These results point to the IL as a major focus for reliability improvement of high-k stacks
{"title":"Detection of trap generation in high-k gate stacks","authors":"C. Young, D. Heh, S. Nadkarni, R. Choi, J. Peterson, H. Harris, J. Sim, S. Krishnan, J. Barnett, E. Vogel, B. Lee, P. Zeitzoff, G.A. Brown, G. Bersuker","doi":"10.1109/IRWS.2005.1609568","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609568","url":null,"abstract":"Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2 /HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate stacks occurs primarily within the interfacial SiO2 layer (IL) on the as-grown \"precursor\" defects most likely caused by the overlaying HfO2 layer. These results point to the IL as a major focus for reliability improvement of high-k stacks","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117093456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609558
J. Michelon, R. Hoofman
In this paper, the impact of moisture on the reliability of porous low-k materials has been investigated. It was found that moisture uptake is more serious for more porous SiOC low-k materials and its presence inside the low-k has a strong impact on dielectric reliability. It has been demonstrated that by eliminating moisture, the leakage current can be significantly decreased and in addition higher breakdown electric fields and longer dielectric lifetimes can be achieved. Therefore, integration of porous low-k materials requires a maximum of attention to prevent moisture uptake at each step during integration and in addition the passivation layers need to be perfectly hermetic in order to maintain good dielectric reliability
{"title":"Impact of moisture on porous low-k reliability","authors":"J. Michelon, R. Hoofman","doi":"10.1109/IRWS.2005.1609558","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609558","url":null,"abstract":"In this paper, the impact of moisture on the reliability of porous low-k materials has been investigated. It was found that moisture uptake is more serious for more porous SiOC low-k materials and its presence inside the low-k has a strong impact on dielectric reliability. It has been demonstrated that by eliminating moisture, the leakage current can be significantly decreased and in addition higher breakdown electric fields and longer dielectric lifetimes can be achieved. Therefore, integration of porous low-k materials requires a maximum of attention to prevent moisture uptake at each step during integration and in addition the passivation layers need to be perfectly hermetic in order to maintain good dielectric reliability","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114794597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609574
M. White, Bing Huang, J. Qin, Z. Gur, M. Talmor, Yuan Chen, J. Heidecker, Due Nguyen, J. Bernstein
As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data
{"title":"Impact of device scaling on deep sub-micron transistor reliability - a study of reliability trends using SRAM","authors":"M. White, Bing Huang, J. Qin, Z. Gur, M. Talmor, Yuan Chen, J. Heidecker, Due Nguyen, J. Bernstein","doi":"10.1109/IRWS.2005.1609574","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609574","url":null,"abstract":"As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133611653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609592
G. Lucovsky
This paper is based on a tutorial/contributed paper pairing that addresses intrinsic limitations for the substitution of high-k gate dielectrics for SiO2 and Si oxynitride alloys in order to extend the scaling of complementary metal oxide semiconductor (CMOS) integrated circuits and systems for at least another 15 to 20 years. An understanding of the intrinsic limitations of the these proposed alternative high-k dielectrics is developed in a systematic way by first addressing the electronic structure differences of these alternative dielectrics with respect to SiO2 and Si oxynitride alloys, and then addressing the issues related to the entire gate stack including: i) interfaces with Si substrate; ii) the gate electrode; and iii) internal dielectric interfaces between the high-k dielectric and interfacial layers, e.g., nitride SiO2 at the Si interface
{"title":"Intrinsic limitations on the performance and reliability of high-k gate dielectrics for advanced silicon devices","authors":"G. Lucovsky","doi":"10.1109/IRWS.2005.1609592","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609592","url":null,"abstract":"This paper is based on a tutorial/contributed paper pairing that addresses intrinsic limitations for the substitution of high-k gate dielectrics for SiO2 and Si oxynitride alloys in order to extend the scaling of complementary metal oxide semiconductor (CMOS) integrated circuits and systems for at least another 15 to 20 years. An understanding of the intrinsic limitations of the these proposed alternative high-k dielectrics is developed in a systematic way by first addressing the electronic structure differences of these alternative dielectrics with respect to SiO2 and Si oxynitride alloys, and then addressing the issues related to the entire gate stack including: i) interfaces with Si substrate; ii) the gate electrode; and iii) internal dielectric interfaces between the high-k dielectric and interfacial layers, e.g., nitride SiO2 at the Si interface","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128838433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609582
J.T.C. Chen, T. Dimitrova, D. Dimitrov, K. Park, D. Schroder
Much work has been done and many papers have been published on gate oxide integrity. The work is largely concentrated on characterization, modeling of oxide degradation and breakdown under stress and measurement techniques. With such extended knowledge and techniques on oxide reliability available, we can make use of that for monitoring wafer quality and process equipment. Here we show that VBD measurements reflect different aspect of oxide characteristics from QBD measurements and each can be used for its corresponding monitoring applications
{"title":"Some applications of V/sub BD/ and Q/sub BD/ tests","authors":"J.T.C. Chen, T. Dimitrova, D. Dimitrov, K. Park, D. Schroder","doi":"10.1109/IRWS.2005.1609582","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609582","url":null,"abstract":"Much work has been done and many papers have been published on gate oxide integrity. The work is largely concentrated on characterization, modeling of oxide degradation and breakdown under stress and measurement techniques. With such extended knowledge and techniques on oxide reliability available, we can make use of that for monitoring wafer quality and process equipment. Here we show that VBD measurements reflect different aspect of oxide characteristics from QBD measurements and each can be used for its corresponding monitoring applications","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124391483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609585
A. E. Yarimbiyik, H. Schafft, R. Allen, M. Zaghloul, D. Blackburn
We have developed a highly versatile simulation program for examining the impact of reduced dimensions on resistivity that goes beyond the work of others, e.g. Fuchs and Mayadas and Shatzkes. The program can simulate the effects of surface and grain-boundary scattering on the resistivity of thin films and lines, either separately or simultaneously. It is used to understand the importance of grain size and how surface and grain boundary scattering impacts the effective resistivity. It predicts how Matthiessen's rule will change with decreasing dimensions, which impacts the ability to determine accurately film thickness and line area from resistance measurements taken at two temperatures.
{"title":"Resistivity of nanometer-scale films and interconnects: model and simulation","authors":"A. E. Yarimbiyik, H. Schafft, R. Allen, M. Zaghloul, D. Blackburn","doi":"10.1109/IRWS.2005.1609585","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609585","url":null,"abstract":"We have developed a highly versatile simulation program for examining the impact of reduced dimensions on resistivity that goes beyond the work of others, e.g. Fuchs and Mayadas and Shatzkes. The program can simulate the effects of surface and grain-boundary scattering on the resistivity of thin films and lines, either separately or simultaneously. It is used to understand the importance of grain size and how surface and grain boundary scattering impacts the effective resistivity. It predicts how Matthiessen's rule will change with decreasing dimensions, which impacts the ability to determine accurately film thickness and line area from resistance measurements taken at two temperatures.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"2003 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128575452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609591
G. Alers
Summary form only given. As interconnects become responsible for a larger portion of signal delays in advanced circuits the pressure for aggressive scaling will increase. Current densities will increase as dimensions are reduced and stress management will be more critical as the compliance of low-k materials decreases. However, reducing the interconnect dimensions tend to degrade reliability as the critical volume associated with a failure decreases. This talk reviewed the conflicting requirements for reliability and product performance and the solutions that are being pursued. Several paths are available for improving electromigration including advanced barriers, copper alloy seed layers and metallic cap layers. However, each of these solutions will come at the cost of line resistance, which is already increasing due to increased scattering in small geometries. Stress migration will become a larger concern at small dimensions because both the absolute stress level and stress gradients will increase at smaller geometries. Reducing the density of the inter-level dielectric will exaggerate these problems due to intrinsically lower adhesion energies and an increased diffusivity of copper, water and ammines in the dielectric. Ultimately, it will be reliability that limits the scaling of interconnects for future nodes.
{"title":"Back end reliability [IC interconnections]","authors":"G. Alers","doi":"10.1109/IRWS.2005.1609591","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609591","url":null,"abstract":"Summary form only given. As interconnects become responsible for a larger portion of signal delays in advanced circuits the pressure for aggressive scaling will increase. Current densities will increase as dimensions are reduced and stress management will be more critical as the compliance of low-k materials decreases. However, reducing the interconnect dimensions tend to degrade reliability as the critical volume associated with a failure decreases. This talk reviewed the conflicting requirements for reliability and product performance and the solutions that are being pursued. Several paths are available for improving electromigration including advanced barriers, copper alloy seed layers and metallic cap layers. However, each of these solutions will come at the cost of line resistance, which is already increasing due to increased scattering in small geometries. Stress migration will become a larger concern at small dimensions because both the absolute stress level and stress gradients will increase at smaller geometries. Reducing the density of the inter-level dielectric will exaggerate these problems due to intrinsically lower adhesion energies and an increased diffusivity of copper, water and ammines in the dielectric. Ultimately, it will be reliability that limits the scaling of interconnects for future nodes.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131211324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-17DOI: 10.1109/IRWS.2005.1609573
R. Wittmann, H. Puchner, L. Hinh, H. Ceric, A. Gehring, S. Selberherr
NBTI has emerged as a major reliability concern for the electrical stability of advanced CMOS technology. We report an experimental and simulation study for the NBTI mechanism in a high-performance p-MOSFET. Various stress experiments were performed in order to analyze the degradation of the key device parameters, V/sub T/ and I/sub Dsat/. The presently leading reaction-diffusion (R-D) model is used to study the interface trap generation based on the diffusion and accumulation of released hydrogen in the gate oxide. The long-time degradation was simulated in order to estimate the NBTI lifetime which depends on the applied gate voltages and frequencies. The lifetime extension under higher frequency operation was analyzed at a typical supply voltage of 1.45V with a tolerance of /spl plusmn/50mV. An unexpected long lifetime extension between six times and twenty times of the DC lifetime was found for an operation with a 10MHz gate signal.
{"title":"Impact of NBTI-driven parameter degradation on lifetime of a 90nm p-MOSFET","authors":"R. Wittmann, H. Puchner, L. Hinh, H. Ceric, A. Gehring, S. Selberherr","doi":"10.1109/IRWS.2005.1609573","DOIUrl":"https://doi.org/10.1109/IRWS.2005.1609573","url":null,"abstract":"NBTI has emerged as a major reliability concern for the electrical stability of advanced CMOS technology. We report an experimental and simulation study for the NBTI mechanism in a high-performance p-MOSFET. Various stress experiments were performed in order to analyze the degradation of the key device parameters, V/sub T/ and I/sub Dsat/. The presently leading reaction-diffusion (R-D) model is used to study the interface trap generation based on the diffusion and accumulation of released hydrogen in the gate oxide. The long-time degradation was simulated in order to estimate the NBTI lifetime which depends on the applied gate voltages and frequencies. The lifetime extension under higher frequency operation was analyzed at a typical supply voltage of 1.45V with a tolerance of /spl plusmn/50mV. An unexpected long lifetime extension between six times and twenty times of the DC lifetime was found for an operation with a 10MHz gate signal.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129840902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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