Charge retention of silicided and unsilicided floating gates in embedded logic nonvolatile memory

Abstract

Some researchers have previously reported that silicide-blocking layers play a key role in retaining charge in embedded DRAM and Flash memory technologies. In this paper, we investigate the retention characteristics for silicided and unsilicided floating gates embedded logic NVM fabricated in a standard 0.25/spl mu/m logic process. In contrast to previous reports, it is found in this work that silicided and unsilicided NVM have equivalent retention for cycled and un-cycled arrays with temperature bake up to 6120 hrs at 135/spl deg/C. As a result, there is more flexibility in optimizing the memory cell area for logic NVM by removing the silicide-blocking layer.