Experimental evaluation of bridge patterns for a high performance microprocessor

S. Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, C. Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee
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引用次数: 13

Abstract

Silicon evaluation of scan patterns, targeting realistic bridges, for a high performance microprocessor is presented. The practicality of generating realistic bridge patterns is demonstrated. Silicon data, with and without functional fails, and in the presence of n-detect tests are presented. Data points to the value of and efficiency of bridge patterns. Data also shows the advantage of using supplemental bridge patterns when compared with supplemental stuck-at patterns.
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一种高性能微处理器电桥模式的实验评估
介绍了一种高性能微处理器针对真实桥的扫描模式的硅评估。证明了生成真实桥型的实用性。硅数据,有和没有功能故障,并在存在n检测测试提出。数据指出了桥梁模式的价值和效率。数据还显示,与补充卡在模式相比,使用补充桥接模式具有优势。
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An economic selecting model for DFT strategies Defect screening using independent component analysis on I/sub DDQ/ Experimental evaluation of bridge patterns for a high performance microprocessor Production test methods for measuring 'out-of-band' interference of ultra wide band (UWB) devices Diagnosis of the failing component in RF receivers through adaptive full-path measurements
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