New minimal March test algorithms are proposed for detection of (all) unlinked static faults in random access memories. In particular, a new minimal March MSS test of complexity I8N is introduced detecting all realistic simple static faults, as March SS (22N), (S. Hamdioui, van de Goor, Rodgers, MTDT 2002).
提出了一种新的最小三月测试算法，用于检测随机存储器中的(所有)非链接静态故障。特别是，引入了一种新的最小复杂度I8N的March MSS测试，用于检测所有实际的简单静态故障，如March SS (22N)， (S. Hamdioui, van de Goor, Rodgers, MTDT 2002)。
{"title":"Minimal March tests for unlinked static faults in random access memories","authors":"Gurgen Harutunyan, V. Vardanian, Y. Zorian","doi":"10.1109/VTS.2005.56","DOIUrl":"https://doi.org/10.1109/VTS.2005.56","url":null,"abstract":"New minimal March test algorithms are proposed for detection of (all) unlinked static faults in random access memories. In particular, a new minimal March MSS test of complexity I8N is introduced detecting all realistic simple static faults, as March SS (22N), (S. Hamdioui, van de Goor, Rodgers, MTDT 2002).","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121047491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a built-in self-test (BIST) scheme for testing ADC s static parameters that include offset error, gain error, integral non-linearity (INL) and differential non-linearity (DNL). The main components in the scheme contain control circuit, differential integrator and test response analyzer (TRA). A system clock pulse is used to trig a counter and inputted to control circuit that regulates the frequency, duty cycle and amplitude of the system clock pulse to output a regulated clock signal (RLK). The RLK is integrated by the integrator to become a called step-ramp stimulus. The correct synchronization between the step-ramp stimulus and the counter output codes is achieved. Then the digital TRA can be designed by analyzing the ADC's output codes and the references of the counter's output codes. With the integration of gradually increasing duty cycles of the RLK to compensate the nonlinear leakage currents depending on the increasing voltages of the integrator, the high accurate step-ramp stimulus is generated. Simulation results show that the accuracies of all step-ramp pieces of the stimulus are within 0.5% LSB.
{"title":"A BIST scheme for testing analog-to-digital converters with digital response analyses","authors":"Y. Wen","doi":"10.1109/VTS.2005.6","DOIUrl":"https://doi.org/10.1109/VTS.2005.6","url":null,"abstract":"This paper presents a built-in self-test (BIST) scheme for testing ADC s static parameters that include offset error, gain error, integral non-linearity (INL) and differential non-linearity (DNL). The main components in the scheme contain control circuit, differential integrator and test response analyzer (TRA). A system clock pulse is used to trig a counter and inputted to control circuit that regulates the frequency, duty cycle and amplitude of the system clock pulse to output a regulated clock signal (RLK). The RLK is integrated by the integrator to become a called step-ramp stimulus. The correct synchronization between the step-ramp stimulus and the counter output codes is achieved. Then the digital TRA can be designed by analyzing the ADC's output codes and the references of the counter's output codes. With the integration of gradually increasing duty cycles of the RLK to compensate the nonlinear leakage currents depending on the increasing voltages of the integrator, the high accurate step-ramp stimulus is generated. Simulation results show that the accuracies of all step-ramp pieces of the stimulus are within 0.5% LSB.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"114 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128975859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SPICE-based calibration of logic gates for a range of values of fanout, charge, and scale factor is presented. A full set of experimental results demonstrate that on average, the model is accurate to within 5% of the results obtained using SPICE with over 100/spl times/ improvement in computational speed. Besides simulation and analysis of SEU-induced transients, the proposed model can be used to perform reliability-aware logic synthesis through the incorporation of robustness metrics to tune cell libraries.
{"title":"Closed-form simulation and robustness models for SEU-tolerant design","authors":"K. Mohanram","doi":"10.1109/VTS.2005.35","DOIUrl":"https://doi.org/10.1109/VTS.2005.35","url":null,"abstract":"A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SPICE-based calibration of logic gates for a range of values of fanout, charge, and scale factor is presented. A full set of experimental results demonstrate that on average, the model is accurate to within 5% of the results obtained using SPICE with over 100/spl times/ improvement in computational speed. Besides simulation and analysis of SEU-induced transients, the proposed model can be used to perform reliability-aware logic synthesis through the incorporation of robustness metrics to tune cell libraries.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124312216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present a new low cost probe card, which enables high speed (500 MHz) memory test on wafer. Since it is difficult to characterize memory devices on wafer at high speed with a low cost probe card, then high speed memory test is usually conducted after assembling packages, although package test requires long lead time for test. We have tested Embedded DRAM at 500 MHz on wafer with the new probe card which has Cantilever needles. The results show that the probe card can be used for memory at-speed test up to 500 MHz.
{"title":"Cantilever type probe card for at-speed memory test on wafer","authors":"H. Iwai, A. Nakayama, Naoko Itoga, Kotaro Omata","doi":"10.1109/VTS.2005.34","DOIUrl":"https://doi.org/10.1109/VTS.2005.34","url":null,"abstract":"In this paper, we present a new low cost probe card, which enables high speed (500 MHz) memory test on wafer. Since it is difficult to characterize memory devices on wafer at high speed with a low cost probe card, then high speed memory test is usually conducted after assembling packages, although package test requires long lead time for test. We have tested Embedded DRAM at 500 MHz on wafer with the new probe card which has Cantilever needles. The results show that the probe card can be used for memory at-speed test up to 500 MHz.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128132518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design of an on-chip spectrum analyzer. A novel architecture is used to mitigate the problems encountered in trying to implement architectures employed in conventional stand-alone instruments on a chip. Specifically, it makes use of a very-low IF architecture, which leads to a highly compact design, that can be used for measuring the frequency content of high frequency on-chip signals. The architecture and design considerations along with an implementation in a 0.18 /spl mu/ CMOS process is described. The design takes up an area of approximately 0.384 mm/sup 2/ with a simulated frequency range of 33 MHz to 3 GHz and a dynamic range of 60 dB.
{"title":"On-chip spectrum analyzer for analog built-in self test","authors":"A. Jose, K. Jenkins, S. Reynolds","doi":"10.1109/VTS.2005.63","DOIUrl":"https://doi.org/10.1109/VTS.2005.63","url":null,"abstract":"This paper presents the design of an on-chip spectrum analyzer. A novel architecture is used to mitigate the problems encountered in trying to implement architectures employed in conventional stand-alone instruments on a chip. Specifically, it makes use of a very-low IF architecture, which leads to a highly compact design, that can be used for measuring the frequency content of high frequency on-chip signals. The architecture and design considerations along with an implementation in a 0.18 /spl mu/ CMOS process is described. The design takes up an area of approximately 0.384 mm/sup 2/ with a simulated frequency range of 33 MHz to 3 GHz and a dynamic range of 60 dB.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133067522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuck
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consumption, and tester channel requirements. With minimal hardware overhead, the architecture provides at least an order of magnitude reduction to each of the above problems. The architecture relies on scan chain segmentation and multiple-hot decoders.
{"title":"Segmented addressable scan architecture","authors":"Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuck","doi":"10.1109/VTS.2005.74","DOIUrl":"https://doi.org/10.1109/VTS.2005.74","url":null,"abstract":"This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consumption, and tester channel requirements. With minimal hardware overhead, the architecture provides at least an order of magnitude reduction to each of the above problems. The architecture relies on scan chain segmentation and multiple-hot decoders.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115556993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper gives an overview of reported design-and process-related electrical performance failure modes for high-speed (> 1 GHz) serial interfaces fabricated using CMOS processes /spl les/130 nm. Effects of various defects on observable performance at the I/O pins are summarized, along with ATE test technology implications.
{"title":"Survey of design and process failure modes for high-speed SerDes in nanometer CMOS","authors":"Cameron Dryden","doi":"10.1109/VTS.2005.79","DOIUrl":"https://doi.org/10.1109/VTS.2005.79","url":null,"abstract":"This paper gives an overview of reported design-and process-related electrical performance failure modes for high-speed (> 1 GHz) serial interfaces fabricated using CMOS processes /spl les/130 nm. Effects of various defects on observable performance at the I/O pins are summarized, along with ATE test technology implications.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117235523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Defect tolerance is an important design consideration for microfluidics-based biochips that are used for safety-critical applications. We propose a defect tolerance methodology based on graceful degradation and dynamic reconfiguration. We first introduce tile-based biochip architecture, which is scalable for large-scale bioassays. A clustered defect model is used to evaluate the graceful degradation method for tile-based biochips. The proposed schemes ensure that the bioassays mapped to a droplet-based microfluidic array during design can be executed on a defective biochip through operation rescheduling and/or resource rebinding. Real-life biochemical procedures, namely polymerase chain reaction (PCR) and multiplexed in-vitro diagnostics on human physiological fluids, are used to evaluate the proposed defect tolerance schemes.
{"title":"Defect tolerance for gracefully-degradable microfluidics-based biochips","authors":"Fei Su, K. Chakrabarty","doi":"10.1109/VTS.2005.39","DOIUrl":"https://doi.org/10.1109/VTS.2005.39","url":null,"abstract":"Defect tolerance is an important design consideration for microfluidics-based biochips that are used for safety-critical applications. We propose a defect tolerance methodology based on graceful degradation and dynamic reconfiguration. We first introduce tile-based biochip architecture, which is scalable for large-scale bioassays. A clustered defect model is used to evaluate the graceful degradation method for tile-based biochips. The proposed schemes ensure that the bioassays mapped to a droplet-based microfluidic array during design can be executed on a defective biochip through operation rescheduling and/or resource rebinding. Real-life biochemical procedures, namely polymerase chain reaction (PCR) and multiplexed in-vitro diagnostics on human physiological fluids, are used to evaluate the proposed defect tolerance schemes.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129455508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan shifts two bits of scan data per clock cycle so the scan clock frequency is halved without increasing the test time. The experimental data show that the proposed technique effectively reduces the test power by two thirds compared with the traditional MUX scan. The presented technique requires very few changes in the existing MUX-scan design for testability methodology and needs no extra computation. The penalties are area overhead and speed degradation.
{"title":"Jump scan: a DFT technique for low power testing","authors":"Min-Hao Chiu, C. Li","doi":"10.1109/VTS.2005.51","DOIUrl":"https://doi.org/10.1109/VTS.2005.51","url":null,"abstract":"This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan shifts two bits of scan data per clock cycle so the scan clock frequency is halved without increasing the test time. The experimental data show that the proposed technique effectively reduces the test power by two thirds compared with the traditional MUX scan. The presented technique requires very few changes in the existing MUX-scan design for testability methodology and needs no extra computation. The penalties are area overhead and speed degradation.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129926030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yi-Shing Chang, S. Chakravarty, Hiep Hoang, N. Thorpe, Khen Wee
The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness.
{"title":"Transition tests for high performance microprocessors","authors":"Yi-Shing Chang, S. Chakravarty, Hiep Hoang, N. Thorpe, Khen Wee","doi":"10.1109/VTS.2005.87","DOIUrl":"https://doi.org/10.1109/VTS.2005.87","url":null,"abstract":"The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126302075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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