H. Chau, D. Pavlidis, G. Ng, K. Tomizawa, D. M. Baker, C. Meaton, J. N. Tothill
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引用次数: 0
Abstract
A novel p/sup -/-n/sup -/ collector design is presented for InP/InGaAs heterostructure bipolar transistors (HBTs). It shows a speed advantage over conventional n/sup -/ collector designs without at the same time being handicapped in terms of breakdown voltage as would normally be the case of traditional special collector designs. The speed and breakdown-speed tradeoff superiority of the p/sup -/-n/sup -/ HBT over the conventional designs are shown and discussed theoretically and experimentally.<>
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