P. Paladhi, Yanyan Zhang, Xianbo Yang, N. Pham, Megan Nguyen, M. Bohra, Junyan Tang, S. Chun, Joshua Myers, W. Becker, D. Dreps
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引用次数: 0
Abstract
With increasing bandwidth and higher transmission data rates in each generation, routing density in motherboards especially under module area have also increased proportionally. Maintaining signal integrity of high-speed channels under such dense routing conditions is becoming more challenging in each new product generation. This paper shows how via to trace coupling in under LGA area can give rise to increased NEXT values thereby causing channel margin loss and failure at high data rates.
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