Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947155
Saikat Mondal, D. Athreya, E. Davies-venn, Zhichao Zhang, K. Aygün
In this paper, we present an improved methodology to achieve good correlation between measured and modeled high frequency data for sockets. The resulting technique was applied to a land grid array (LGA) socket, designed to provide a detachable solution between a microelectronic package and a printed circuit board (PCB), while simultaneously satisfying the stringent electrical requirements for high speed signaling. Test vehicles were assembled with surface mount LGA sockets on test boards and a removable test package. 4-port and 12-port S-parameter measurements were performed on the test vehicle assembly. The socket only insertion loss and return loss performance was extracted using a de-embedding process. A good correlation was achieved between de-embedded measured and modeled differential-ended (DE) insertion loss (IL) data from DC to 16 GHz. For the first time such good correlation for de-embedded high frequency socket data has been reported as per the authors' best knowledge.
{"title":"An Improved Methodology for High Frequency Socket Performance Characterization","authors":"Saikat Mondal, D. Athreya, E. Davies-venn, Zhichao Zhang, K. Aygün","doi":"10.1109/EPEPS53828.2022.9947155","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947155","url":null,"abstract":"In this paper, we present an improved methodology to achieve good correlation between measured and modeled high frequency data for sockets. The resulting technique was applied to a land grid array (LGA) socket, designed to provide a detachable solution between a microelectronic package and a printed circuit board (PCB), while simultaneously satisfying the stringent electrical requirements for high speed signaling. Test vehicles were assembled with surface mount LGA sockets on test boards and a removable test package. 4-port and 12-port S-parameter measurements were performed on the test vehicle assembly. The socket only insertion loss and return loss performance was extracted using a de-embedding process. A good correlation was achieved between de-embedded measured and modeled differential-ended (DE) insertion loss (IL) data from DC to 16 GHz. For the first time such good correlation for de-embedded high frequency socket data has been reported as per the authors' best knowledge.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127360717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947153
Nikhita Baladari, R. Wenzel
Integration of high-speed digital electronics and high-frequency radar channels in a package with limited layers can result in compromised return paths and degraded signal integrity. In this paper, we designed a digital block over a 77 GHz RF channel and used different package models to evaluate the digital coupling between the digital and RF blocks and the effect on their signal integrity.
{"title":"Design and Optimization of High-Speed Digital Bus Over RF Channel","authors":"Nikhita Baladari, R. Wenzel","doi":"10.1109/EPEPS53828.2022.9947153","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947153","url":null,"abstract":"Integration of high-speed digital electronics and high-frequency radar channels in a package with limited layers can result in compromised return paths and degraded signal integrity. In this paper, we designed a digital block over a 77 GHz RF channel and used different package models to evaluate the digital coupling between the digital and RF blocks and the effect on their signal integrity.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128448611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947183
Fabio A. Ruiz-Molina, Jingbo Li, Kai Xiao
Previous studies have shown PAM4 signaling is ~3x more sensitive to noise interference comparing to NRZ mode. Furthermore, because of the backward compatibility requirement, PCIe needs to support both PAM4 and NRZ signaling mode. As a result, the crosstalk scenario can be much more complicated than a sole signal modulation mode. In this paper, we present a thorough analysis for the crosstalk impact on PCIe 6.0 link (PAM4) with backward compatibility of previous generations, such as PCIe 5.0 (NRZ). Several key factors, including voltage swing, equalization, modulation type, number of aggressors and port partition or bifurcations, have been studied to show their impact on the crosstalk behavior and the related effect on the full link performance. This methodology will serve as a guideline to thoroughly study the crosstalk impact for platforms with PCIe 6.0 links. It is demonstrated that, after including all the considered variables about the crosstalk, the total degradation could add up to ~22% for EH and ~19% for EW.
{"title":"Crosstalk Analysis for PCIe 6.0 (PAM4) Under Different Transmitter Conditions","authors":"Fabio A. Ruiz-Molina, Jingbo Li, Kai Xiao","doi":"10.1109/EPEPS53828.2022.9947183","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947183","url":null,"abstract":"Previous studies have shown PAM4 signaling is ~3x more sensitive to noise interference comparing to NRZ mode. Furthermore, because of the backward compatibility requirement, PCIe needs to support both PAM4 and NRZ signaling mode. As a result, the crosstalk scenario can be much more complicated than a sole signal modulation mode. In this paper, we present a thorough analysis for the crosstalk impact on PCIe 6.0 link (PAM4) with backward compatibility of previous generations, such as PCIe 5.0 (NRZ). Several key factors, including voltage swing, equalization, modulation type, number of aggressors and port partition or bifurcations, have been studied to show their impact on the crosstalk behavior and the related effect on the full link performance. This methodology will serve as a guideline to thoroughly study the crosstalk impact for platforms with PCIe 6.0 links. It is demonstrated that, after including all the considered variables about the crosstalk, the total degradation could add up to ~22% for EH and ~19% for EW.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129104381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947105
Yun-Ho Lee, Dongho Kim, Sang-Hyup Kwak, JeongHun Baek, Kyoungsun Kim, Sung Joo Park, Jeonghyeon Cho, H. Song
In DDR5 dual-in-line-memory-modules (DIMMs), a registering clock driver (RCD) receives control, address, clock signals from CPU and re-drives them to dynamic random access memories (DRAMs) through transmission lines on printed circuit board (PCB). Especially, clock signals operate at double data rate (DDR) which makes it substantially difficult to guarantee signal integrity (SI), whereas control, address signals operate at single data rate (SDR). As of now, JEDEC standards prescribes that the effective characteristic impedance of clock signals be as low as 22.5 Ohm for DDR5 DIMMs. With the strict restriction on the physical dimensions of PCB set forth by JEDEC, along with the fact high permittivity materials have already reached their limit, there is a limit to achieve low characteristic impedance with current PCB fabrication processes including increasing signal width, use of high permittivity materials and close reference plane. Therefore, we propose a novel differential signal routing method so as to achieve low characteristic impedance, and consequently wider bandwidth for high-speed and large-capacity DDR5 DIMMs. With the proposed structure on DIMM, the system bandwidth can be extended by 12%, allowing 7.2Gbps operation of DDR5 Mono DRAM.
{"title":"A Novel Differential Signal Routing Method for High-Speed and Large-Capacity DDR5 Dual-In-Line Memory Module","authors":"Yun-Ho Lee, Dongho Kim, Sang-Hyup Kwak, JeongHun Baek, Kyoungsun Kim, Sung Joo Park, Jeonghyeon Cho, H. Song","doi":"10.1109/EPEPS53828.2022.9947105","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947105","url":null,"abstract":"In DDR5 dual-in-line-memory-modules (DIMMs), a registering clock driver (RCD) receives control, address, clock signals from CPU and re-drives them to dynamic random access memories (DRAMs) through transmission lines on printed circuit board (PCB). Especially, clock signals operate at double data rate (DDR) which makes it substantially difficult to guarantee signal integrity (SI), whereas control, address signals operate at single data rate (SDR). As of now, JEDEC standards prescribes that the effective characteristic impedance of clock signals be as low as 22.5 Ohm for DDR5 DIMMs. With the strict restriction on the physical dimensions of PCB set forth by JEDEC, along with the fact high permittivity materials have already reached their limit, there is a limit to achieve low characteristic impedance with current PCB fabrication processes including increasing signal width, use of high permittivity materials and close reference plane. Therefore, we propose a novel differential signal routing method so as to achieve low characteristic impedance, and consequently wider bandwidth for high-speed and large-capacity DDR5 DIMMs. With the proposed structure on DIMM, the system bandwidth can be extended by 12%, allowing 7.2Gbps operation of DDR5 Mono DRAM.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124218380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947126
Jiwoong Jeon, Shivani Joshi, Daniel de Araujo, B. Mutnury
In printed circuit boards, vias are needed when signals make layer transitions. Typically, via transitions are defined through padstacks. These padstacks provide geometrical manufacturing characteristics of the transitions such as via drill size, pad size, antipad size and thermal tolerance. Differential via design consists of padstack definition and relative positioning to other padstacks such as signal and reference as well as entry and exit trace parameters. At high speeds, vias cause reflections if they are not well designed. When stack-ups have a lot of signal layers, optimizing via padstack for each signal transition is going to be cumbersome. Using a padstack optimized for one signal transition on other transitions may degrade signal performance. In this work, a simultaneous codimensional optimization to differential via padstack designs is proposed to optimize a single padstack definition so that it can handle multiple entry/exit layer transitions.
{"title":"Codimensional Optimization of Differential Via Padstacks","authors":"Jiwoong Jeon, Shivani Joshi, Daniel de Araujo, B. Mutnury","doi":"10.1109/EPEPS53828.2022.9947126","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947126","url":null,"abstract":"In printed circuit boards, vias are needed when signals make layer transitions. Typically, via transitions are defined through padstacks. These padstacks provide geometrical manufacturing characteristics of the transitions such as via drill size, pad size, antipad size and thermal tolerance. Differential via design consists of padstack definition and relative positioning to other padstacks such as signal and reference as well as entry and exit trace parameters. At high speeds, vias cause reflections if they are not well designed. When stack-ups have a lot of signal layers, optimizing via padstack for each signal transition is going to be cumbersome. Using a padstack optimized for one signal transition on other transitions may degrade signal performance. In this work, a simultaneous codimensional optimization to differential via padstack designs is proposed to optimize a single padstack definition so that it can handle multiple entry/exit layer transitions.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114391534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947145
Jie Chen, R. Murugan, Sooping Saw, Francisco Lauzurique, J. Broze, Craig Greenberg, Alex Triano, B. Nayak, H. Muniganti, Joe Sivaswamy, D. Gope
Applications of power electronics that integrate high-switching isolated gate drivers in switch mode power converters create excessive transient di/dt and dv/dt loops that exacerbate electromagnetic emissions. In this work, we developed a robust system-level coupled circuit-to-electromagnetic modeling and analysis methodology to predict the CISPR 25 radiated emission performance of a reinforced isolated switch driver during product development. The coupled method accurately captures the electromagnetic interactions between the nonlinear time-variant switchers and the system. Preliminary silicon validation measurements on an automotive high-switching isolated switch driver with an integrated power supply are presented to validate the integrity of the predictive modeling methodology. In an EMC pre-compliance lab, good correlations between modeling and measurements are achieved (i.e., within +/- 3dB for resonant peaks within the frequency band of 30MHz − 1GHz). The predictive EMC modeling methodology can be implemented to assess the performance of the initial silicon design during early IC development.
{"title":"CISPR 25 Radiated Emission Simulation and Measurement Correlation of an Automotive Reinforced Isolated Switch Driver","authors":"Jie Chen, R. Murugan, Sooping Saw, Francisco Lauzurique, J. Broze, Craig Greenberg, Alex Triano, B. Nayak, H. Muniganti, Joe Sivaswamy, D. Gope","doi":"10.1109/EPEPS53828.2022.9947145","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947145","url":null,"abstract":"Applications of power electronics that integrate high-switching isolated gate drivers in switch mode power converters create excessive transient di/dt and dv/dt loops that exacerbate electromagnetic emissions. In this work, we developed a robust system-level coupled circuit-to-electromagnetic modeling and analysis methodology to predict the CISPR 25 radiated emission performance of a reinforced isolated switch driver during product development. The coupled method accurately captures the electromagnetic interactions between the nonlinear time-variant switchers and the system. Preliminary silicon validation measurements on an automotive high-switching isolated switch driver with an integrated power supply are presented to validate the integrity of the predictive modeling methodology. In an EMC pre-compliance lab, good correlations between modeling and measurements are achieved (i.e., within +/- 3dB for resonant peaks within the frequency band of 30MHz − 1GHz). The predictive EMC modeling methodology can be implemented to assess the performance of the initial silicon design during early IC development.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116072819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947164
Shucheng Zheng, V. Okhmatovski
New closed-form expression for quasi-static 2-D Green's function of fully-shielded layered medium is proposed. Along the vertical direction of the medium stratification the spectrum of the Green's function can be obtained through the 1-D ordinary differential equation and expressed as pole-residual form. This rational function representation of the spectrum allows to evaluate space domain Green's function in layered medium shielded from top and bottom with horizontal ground planes in a closed-form. This closed-form expression allows to analytically add up contributions from infinite number of source images with respect to the vertical side walls of the rectangular enclosure, hence, producing the new closed-form expression for the 2-D Green's function of rectangular enclosure vertically filled with multilayered medium. Availability of such Green's functions enable construction of integral equation based magneto-quasi-static and electro-quasi-static 2-D extractors. Such 2-D magneto-quasi-static extractor based on solution of Surface-Volume-Surface Electric Field Integral Equation (SVS-EFIE) for multi-conductor transmission lines (MTLs) situated in shielded layered media is demonstrated.
{"title":"Novel Closed-Form 2-D Green's Function of Shielded Layered Media And Its Use in Transmission Lines Inductance Extraction","authors":"Shucheng Zheng, V. Okhmatovski","doi":"10.1109/EPEPS53828.2022.9947164","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947164","url":null,"abstract":"New closed-form expression for quasi-static 2-D Green's function of fully-shielded layered medium is proposed. Along the vertical direction of the medium stratification the spectrum of the Green's function can be obtained through the 1-D ordinary differential equation and expressed as pole-residual form. This rational function representation of the spectrum allows to evaluate space domain Green's function in layered medium shielded from top and bottom with horizontal ground planes in a closed-form. This closed-form expression allows to analytically add up contributions from infinite number of source images with respect to the vertical side walls of the rectangular enclosure, hence, producing the new closed-form expression for the 2-D Green's function of rectangular enclosure vertically filled with multilayered medium. Availability of such Green's functions enable construction of integral equation based magneto-quasi-static and electro-quasi-static 2-D extractors. Such 2-D magneto-quasi-static extractor based on solution of Surface-Volume-Surface Electric Field Integral Equation (SVS-EFIE) for multi-conductor transmission lines (MTLs) situated in shielded layered media is demonstrated.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122572441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947173
Seunghyup Han, O. W. Bhatti, Madhavan Swaminathan
This paper proposes a deep deterministic policy gradient (DDPG) based method to optimize the power plane in power delivery networks (PDNs). The proposed method considers the degrees of freedom of a plane design in a layer, determining the parameters for creating a power plane. The results show that the proposed method can provide an optimized power plane design even in a plane layer with a restricted region.
{"title":"Reinforcement Learning for the Optimization of Power Plane Designs in Power Delivery Networks","authors":"Seunghyup Han, O. W. Bhatti, Madhavan Swaminathan","doi":"10.1109/EPEPS53828.2022.9947173","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947173","url":null,"abstract":"This paper proposes a deep deterministic policy gradient (DDPG) based method to optimize the power plane in power delivery networks (PDNs). The proposed method considers the degrees of freedom of a plane design in a layer, determining the parameters for creating a power plane. The results show that the proposed method can provide an optimized power plane design even in a plane layer with a restricted region.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125386150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947166
Hyunwook Park, Taein Shin, Seongguk Kim, Daehwan Lho, Boogyo Sim, Jinwook Song, Kyubong Kong, Joungho Kim
In this paper, we first propose a scalable transformer network-based reinforcement learning (RL) method for power supply induced jitter (PSIJ) optimization in high bandwidth memory (HBM). The proposed method can provide an optimal power distribution network (PDN) decoupling capacitor (decap) design to satisfy the target PSIJ with the minimum number of NMOS decaps. For the given number of decaps, the network is trained to maximize the impedance reduction from 10 MHz to 20 GHz compared to the initial PDN. Also, the network has scalability on the number of decap assignments. Therefore, for given any number of decaps, the scalable network can provide minimized PDN impedance profiles by one inference without re-training. Then, by increasing the decap assignments, the network can find out the minimum number to meet the given target PSIJ. For verification, the proposed network is applied to the HBM2 I/O interface. The network successfully provides the optimized decap designs to satisfy the given target PSIJ values.
{"title":"Scalable Transformer Network-based Reinforcement Learning Method for PSIJ Optimization in HBM","authors":"Hyunwook Park, Taein Shin, Seongguk Kim, Daehwan Lho, Boogyo Sim, Jinwook Song, Kyubong Kong, Joungho Kim","doi":"10.1109/EPEPS53828.2022.9947166","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947166","url":null,"abstract":"In this paper, we first propose a scalable transformer network-based reinforcement learning (RL) method for power supply induced jitter (PSIJ) optimization in high bandwidth memory (HBM). The proposed method can provide an optimal power distribution network (PDN) decoupling capacitor (decap) design to satisfy the target PSIJ with the minimum number of NMOS decaps. For the given number of decaps, the network is trained to maximize the impedance reduction from 10 MHz to 20 GHz compared to the initial PDN. Also, the network has scalability on the number of decap assignments. Therefore, for given any number of decaps, the scalable network can provide minimized PDN impedance profiles by one inference without re-training. Then, by increasing the decap assignments, the network can find out the minimum number to meet the given target PSIJ. For verification, the proposed network is applied to the HBM2 I/O interface. The network successfully provides the optimized decap designs to satisfy the given target PSIJ values.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127469480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/EPEPS53828.2022.9947171
Shinyoun Park, Vinod Arjun Huddar
From DDR3 and beyond, the fly-by has been widely used as it can support high data rate operations by providing smaller trace stubs and capacitive loadings. Even so, beyond a certain number of loadings, the fly-by also starts to have trouble in keeping up with high data rates. To accommodate larger loadings, either data rate needs to be reduced or advanced equalization techniques are required. To address this limitation of fly-by topology, we propose advanced fly-by topology routing.
{"title":"Advanced Fly-By Routing Topology for Gbps DDR5 Systems","authors":"Shinyoun Park, Vinod Arjun Huddar","doi":"10.1109/EPEPS53828.2022.9947171","DOIUrl":"https://doi.org/10.1109/EPEPS53828.2022.9947171","url":null,"abstract":"From DDR3 and beyond, the fly-by has been widely used as it can support high data rate operations by providing smaller trace stubs and capacitive loadings. Even so, beyond a certain number of loadings, the fly-by also starts to have trouble in keeping up with high data rates. To accommodate larger loadings, either data rate needs to be reduced or advanced equalization techniques are required. To address this limitation of fly-by topology, we propose advanced fly-by topology routing.","PeriodicalId":284818,"journal":{"name":"2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"48 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130420707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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