A VLSI Layout Legalization Technique Based on a Graph Fixing Algorithm

Abstract

This paper describes a novel graph fixing algorithm which can be used to fix the design constraint violations for a VLSI layout. Layouts are designed so that the process design rule and user specified constraints must be satisfied. Custom layout methodologies and process design rule migration activities introduce rule and constraint violations in layouts. Traditionally, layout compaction technique based on minimal area criterion is used to solve layout constraint violation problem. Unfortunately such layout compaction technique often fail in real designs since the layout often changed significantly and resulted in circuit performance degeneracy after layout compaction. Recently, a minimum layout perturbation was proposed to overcome the aforementioned drawback. The layout legalization was formulated as a linear programming problem which objective function was the summation of the perturbation of shapes. Such works reduced the impact on circuit performance greatly. In this paper, based on the concept of minimum layout perturbation, a more efficient graph fixing algorithm is proposed to solve layout legalization problem. This algorithm has been implemented as a part of Lakertrade AutoCorrect function and demonstrated the efficiency and feasibility for several real designs