Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258114
D. Lie, J. Kennedy, D. Livezey, B. Yang, T. Robinson, N. Sornin, C. Saint, L. Larson
This paper discusses the RF circuit and system design considerations for W-CDMA homodyne receiver on NF, IIP2, IIP3, LO/TX leakage, I-Q mismatch, DC offsets, etc. A zero-IF receiver front-end SiGe BiCMOS IC is designed, packaged and thoroughly characterized by a set of system-level performance tests across the full frequency band of operation. The measured worst-case cascaded NF for the receiver IC across all channels is 4.3 dB at the max. gain mode, and the in-band/out-of-band IIP2 and IIP3 are +37/+93 and -16.5/+5 dBm, respectively. The I/Q channels exhibit a small mismatch in magnitude (<0.1dB) and in phase (<1deg) without calibration. The receiver RF front-end (i.e., LNA+VGA+ I/Q mixers) draws ~45mW. The system tests results on BER, P1dB, IM2, IM3, and desensing show that the RFIC meets all of the necessary parameters of W-CDMA receiver system specs at room temperature with margin, validating the RF IC block-level circuit design and providing valuable RF-SoC design insights
{"title":"Circuit and System Design for a Homodyne W-CDMA Front-End Receiver RF IC","authors":"D. Lie, J. Kennedy, D. Livezey, B. Yang, T. Robinson, N. Sornin, C. Saint, L. Larson","doi":"10.1109/VDAT.2006.258114","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258114","url":null,"abstract":"This paper discusses the RF circuit and system design considerations for W-CDMA homodyne receiver on NF, IIP2, IIP3, LO/TX leakage, I-Q mismatch, DC offsets, etc. A zero-IF receiver front-end SiGe BiCMOS IC is designed, packaged and thoroughly characterized by a set of system-level performance tests across the full frequency band of operation. The measured worst-case cascaded NF for the receiver IC across all channels is 4.3 dB at the max. gain mode, and the in-band/out-of-band IIP2 and IIP3 are +37/+93 and -16.5/+5 dBm, respectively. The I/Q channels exhibit a small mismatch in magnitude (<0.1dB) and in phase (<1deg) without calibration. The receiver RF front-end (i.e., LNA+VGA+ I/Q mixers) draws ~45mW. The system tests results on BER, P1dB, IM2, IM3, and desensing show that the RFIC meets all of the necessary parameters of W-CDMA receiver system specs at room temperature with margin, validating the RF IC block-level circuit design and providing valuable RF-SoC design insights","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116814241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258156
S. Tontisirin, R. Tielert
A 1-2.25 Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18mum CMOS technology. It has an active area of 0.7 mm2 and consumes 100mW at 1.8V supply. The CDR has low jitter operation in a wide frequency range from 1-2.25 Gb/s. Measurement of bit-error rate is less than 10-12 for 2.25 Gb/s incoming data 27-1 PRBS, jitter peak-to-peak of 0.7 unit interval(UI) modulation at 10 MHz
{"title":"Gb/s CMOS 1-4th-rate CDR with Frequency Detector and Skew calibration","authors":"S. Tontisirin, R. Tielert","doi":"10.1109/VDAT.2006.258156","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258156","url":null,"abstract":"A 1-2.25 Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18mum CMOS technology. It has an active area of 0.7 mm2 and consumes 100mW at 1.8V supply. The CDR has low jitter operation in a wide frequency range from 1-2.25 Gb/s. Measurement of bit-error rate is less than 10-12 for 2.25 Gb/s incoming data 27-1 PRBS, jitter peak-to-peak of 0.7 unit interval(UI) modulation at 10 MHz","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126878384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258145
Meng-Chiou Wu, Shr-Cheng Tsai, Rung-Bin Lin
Floorplanning chips in more than one reticle for multi-project wafers has not been investigated. In this paper, we propose two approaches to this problem. We first formulate this problem with preselected reticle sizes as a mixed-integer linear programming (MILP) model. We then propose a compatibility-driven B*-tree dissection search (CBTDS) heuristic for it. Experiments for floorplanning chips in two reticles show that the MILP model is too complex to render good results, while CBTDS is very effective and efficient. Compared to a naive solution, CBTDS obtains a floorplan that uses 37% fewer wafers
{"title":"Floorplanning Multiple Reticles for Multi-project Wafers","authors":"Meng-Chiou Wu, Shr-Cheng Tsai, Rung-Bin Lin","doi":"10.1109/VDAT.2006.258145","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258145","url":null,"abstract":"Floorplanning chips in more than one reticle for multi-project wafers has not been investigated. In this paper, we propose two approaches to this problem. We first formulate this problem with preselected reticle sizes as a mixed-integer linear programming (MILP) model. We then propose a compatibility-driven B*-tree dissection search (CBTDS) heuristic for it. Experiments for floorplanning chips in two reticles show that the MILP model is too complex to render good results, while CBTDS is very effective and efficient. Compared to a naive solution, CBTDS obtains a floorplan that uses 37% fewer wafers","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114726273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258179
Chin-Hsien Yen, Win-Ming Chang, Kuo-Hua Cheng, C. Jou
This paper presents a new low voltage CMOS micromixer for 2.45GHz applications, which operates at 1V supply voltage. The new low voltage CMOS micromixer topology modified from basic BJT micromixer uses coupling capacitors to feed the RF signal so as to bias the two transistors in RF stage separately with lower voltage. The charge injection method is also adopted to improve the conversion gain and linearity under low voltage operation. With a power consumption of 1.72 mW the measurement shows voltage gain of 8.28 dB, input 1dB compression point of -5.63 dBm and input third-order intercept point of 4.21 dBm
{"title":"A New Low Voltage CMOS Micromixer for 2.45GHz Applications","authors":"Chin-Hsien Yen, Win-Ming Chang, Kuo-Hua Cheng, C. Jou","doi":"10.1109/VDAT.2006.258179","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258179","url":null,"abstract":"This paper presents a new low voltage CMOS micromixer for 2.45GHz applications, which operates at 1V supply voltage. The new low voltage CMOS micromixer topology modified from basic BJT micromixer uses coupling capacitors to feed the RF signal so as to bias the two transistors in RF stage separately with lower voltage. The charge injection method is also adopted to improve the conversion gain and linearity under low voltage operation. With a power consumption of 1.72 mW the measurement shows voltage gain of 8.28 dB, input 1dB compression point of -5.63 dBm and input third-order intercept point of 4.21 dBm","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127782378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258167
Tzong-Yen Lin, Yu-Ting Hung, Rong-Guey Chang
This paper presents an efficient hardware/software partitioning approach that target at embedded multiprocessor systems with time, area, and power constraints. Our approach is performed in two phases. In the partitioning phase, for an embedded system with p software components and q hardware components, recursive spectral bisection (RSB) has been used to partition an application program into n well-balanced and connected blocks with low communication cost. These blocks are mapped into software components and then tasks in software components will be moved to hardware components to meet the deadline constraint. In the scheduling phase, we derive an approach to reduce the system cost in connection with power and hardware area by exchanging tasks between software and hardware components. Experimental results show that our approach is effective for embedded multiprocessor systems
{"title":"Efficient Hardware/Software Partitioning Approach for Embedded Multiprocessor Systems","authors":"Tzong-Yen Lin, Yu-Ting Hung, Rong-Guey Chang","doi":"10.1109/VDAT.2006.258167","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258167","url":null,"abstract":"This paper presents an efficient hardware/software partitioning approach that target at embedded multiprocessor systems with time, area, and power constraints. Our approach is performed in two phases. In the partitioning phase, for an embedded system with p software components and q hardware components, recursive spectral bisection (RSB) has been used to partition an application program into n well-balanced and connected blocks with low communication cost. These blocks are mapped into software components and then tasks in software components will be moved to hardware components to meet the deadline constraint. In the scheduling phase, we derive an approach to reduce the system cost in connection with power and hardware area by exchanging tasks between software and hardware components. Experimental results show that our approach is effective for embedded multiprocessor systems","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126389001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258111
C.L. Lee, K. Hsiao, Min-Chung Chou
A mega pixel image signal processor (ISP) with low voltage differential serial interface is presented. subLVDS interface has lower voltage swing and lower power consumption advantages over a normal LVDS interface. Both subLVDS driver and receiver are implemented in this ISP chip to reduce the I/O pin count. A synchronization layer is designed to cover both non-compressed and compressed image data transfer on the high-speed serial data link. This chip is designed with a pure logic process in 0.18 mum CMOS technology. The subLVDS driver can operate at a transfer rate up to 625Mbps
提出了一种具有低电压差分串行接口的百万像素图像信号处理器。与普通LVDS接口相比，subLVDS接口具有电压摆幅小、功耗低的优点。为了减少I/O引脚数，在该ISP芯片中实现了subvds驱动程序和接收器。同步层被设计用于覆盖高速串行数据链路上的非压缩和压缩图像数据传输。该芯片采用0.18 μ m CMOS技术，采用纯逻辑工艺设计。subblvds驱动程序可以以高达625Mbps的传输速率运行
{"title":"A Low Power Mobile Camera Processor Design with SubLVDS Interface","authors":"C.L. Lee, K. Hsiao, Min-Chung Chou","doi":"10.1109/VDAT.2006.258111","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258111","url":null,"abstract":"A mega pixel image signal processor (ISP) with low voltage differential serial interface is presented. subLVDS interface has lower voltage swing and lower power consumption advantages over a normal LVDS interface. Both subLVDS driver and receiver are implemented in this ISP chip to reduce the I/O pin count. A synchronization layer is designed to cover both non-compressed and compressed image data transfer on the high-speed serial data link. This chip is designed with a pure logic process in 0.18 mum CMOS technology. The subLVDS driver can operate at a transfer rate up to 625Mbps","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131099268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258181
J.P. Liu, P. R. Verma, S. Chu, S.Q. Zhang, W. Loh, K. Leong, H.L. Siew, D. Sohn, L. Hsia, S. Decoutere, M. Xu, K. van Wichelen, R. Loo
We show that the incorporation of interstitial C impacts the base current ideality in SiGe:C HBTs fabricated in 0.18mum SiGe BiCMOS process. SiGe:C epi layers with the same structural and processing parameters but with less interstitial C obtained by adjusting growth conditions have better base current ideality. It is observed that the interstitial C in the emitter/base depletion region, rather than that in the neutral base region, leads to the base current non-ideality. Optimization of C substitution and profile leads to less recombination as well as good B diffusion control thus good device performance
我们发现，在0.18 μ m SiGe BiCMOS工艺中加入间隙C会影响SiGe:C HBTs的基极电流理想性。调整生长条件得到的结构和工艺参数相同但间隙C较小的SiGe:C外延层具有较好的基极电流理想性。我们观察到，基极损耗区的间隙C，而不是中性基极区的间隙C，导致基极电流的非理想性。通过优化C取代和构型，可以减少复合，控制B扩散，从而提高器件性能
{"title":"Impact of Interstitial Carbon on Base Current Ideality in SiGe:C Heterojunction Bipolar Transistors","authors":"J.P. Liu, P. R. Verma, S. Chu, S.Q. Zhang, W. Loh, K. Leong, H.L. Siew, D. Sohn, L. Hsia, S. Decoutere, M. Xu, K. van Wichelen, R. Loo","doi":"10.1109/VDAT.2006.258181","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258181","url":null,"abstract":"We show that the incorporation of interstitial C impacts the base current ideality in SiGe:C HBTs fabricated in 0.18mum SiGe BiCMOS process. SiGe:C epi layers with the same structural and processing parameters but with less interstitial C obtained by adjusting growth conditions have better base current ideality. It is observed that the interstitial C in the emitter/base depletion region, rather than that in the neutral base region, leads to the base current non-ideality. Optimization of C substitution and profile leads to less recombination as well as good B diffusion control thus good device performance","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133515033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258116
Yun-Hsueh Chuang, Shao-Hua Lee, Chien-Feng Lee, S. Jang, M. Juang
This paper presents a new voltage controlled oscillator (VCO) topology for radio frequency operation. The low phase noise differential CMOS VCO uses capacitive degeneration and transformer coupling between the gate and source of the negative conductance transistor. An on chip transformer in positive feedback is used to increase the voltage swing in resonator and to improve the phase noise. The VCO is tunable from 2.85 GHz to 3.35 GHz with 16% tuning range, and has been fabricated with 0.18mum CMOS technology. The measured phase noise at 1 MHz offset is -119 dBc/Hz at the operation frequency of 3 GHz. The circuit draws 10 mA from a 1.8V supply
提出了一种新的用于射频工作的压控振荡器(VCO)拓扑结构。低相位噪声差分CMOS压控振荡器采用负导晶体管栅极和源极之间的电容退化和变压器耦合。采用正反馈的片上变压器增加了谐振腔内的电压摆幅，改善了相位噪声。该VCO可在2.85 GHz至3.35 GHz范围内调谐，调谐范围为16%，采用0.18 μ m CMOS技术制造。工作频率为3ghz时，测量到1mhz偏移时的相位噪声为-119 dBc/Hz。该电路从1.8V电源提取10 mA
{"title":"A New CMOS VCO Topology with Capacitive Degeneration and Transformer Feedback","authors":"Yun-Hsueh Chuang, Shao-Hua Lee, Chien-Feng Lee, S. Jang, M. Juang","doi":"10.1109/VDAT.2006.258116","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258116","url":null,"abstract":"This paper presents a new voltage controlled oscillator (VCO) topology for radio frequency operation. The low phase noise differential CMOS VCO uses capacitive degeneration and transformer coupling between the gate and source of the negative conductance transistor. An on chip transformer in positive feedback is used to increase the voltage swing in resonator and to improve the phase noise. The VCO is tunable from 2.85 GHz to 3.35 GHz with 16% tuning range, and has been fabricated with 0.18mum CMOS technology. The measured phase noise at 1 MHz offset is -119 dBc/Hz at the operation frequency of 3 GHz. The circuit draws 10 mA from a 1.8V supply","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116461228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258147
Yi-Wei Lin, Yao-Wen Chang
Temperature, as well as electromigration (EM), area, timing, and power, has become one of the most important concerns in nanometer circuit design. In this paper, we model the effects of thermal on both interconnect delay and EM reliability. Applying the least square estimator (LSE) method, we develop a posynomial formula to approximate interconnect temperature and present an algorithm to optimally solve the simultaneous interconnect temperature, EM, area, delay, and power optimization by sizing circuit components based on Lagrangian relaxation. Experimental results show that our algorithm is very effective, efficient, and economical
{"title":"Thermal-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing","authors":"Yi-Wei Lin, Yao-Wen Chang","doi":"10.1109/VDAT.2006.258147","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258147","url":null,"abstract":"Temperature, as well as electromigration (EM), area, timing, and power, has become one of the most important concerns in nanometer circuit design. In this paper, we model the effects of thermal on both interconnect delay and EM reliability. Applying the least square estimator (LSE) method, we develop a posynomial formula to approximate interconnect temperature and present an algorithm to optimally solve the simultaneous interconnect temperature, EM, area, delay, and power optimization by sizing circuit components based on Lagrangian relaxation. Experimental results show that our algorithm is very effective, efficient, and economical","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125964104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-26DOI: 10.1109/VDAT.2006.258119
Keunwoo Kim, K. Das, C. Chuang
This paper presents a new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual ground bounce for the proposed scheme is also presented
{"title":"Novel High-Density Data-Retention Power Gating Structure Using a Four-Terminal Double-Gate Device","authors":"Keunwoo Kim, K. Das, C. Chuang","doi":"10.1109/VDAT.2006.258119","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258119","url":null,"abstract":"This paper presents a new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual ground bounce for the proposed scheme is also presented","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127455823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：