P. Eyben, T. Chiarella, S. Kubicek, H. Bender, O. Richard, J. Mitard, A. Mocuta, N. Horiguchi, A. Thean
{"title":"Scalpel soft retrace scanning spreading resistance microscopy for 3D-carrier profiling in sub-10nm WFIN FinFET","authors":"P. Eyben, T. Chiarella, S. Kubicek, H. Bender, O. Richard, J. Mitard, A. Mocuta, N. Horiguchi, A. Thean","doi":"10.1109/IEDM.2015.7409693","DOIUrl":null,"url":null,"abstract":"Site-specific real three-dimensional (3D) carrier profiling in sub-10nm WFIN devices is demonstrated for the first time. Extension-gate overlap, active dopant concentration and distribution inside extensions and epi source/drain are observed with 1 nm-spatial resolution along X, Y and Z-directions. Using this new technique providing full 3D-carrier mapping we analyzed different processing flows for sub-10nm fin width FinFETs, identified possible failure mechanisms, and demonstrated the direct link between improved performance and 3D-carrier distribution at the nm-scale.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2015.7409693","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Site-specific real three-dimensional (3D) carrier profiling in sub-10nm WFIN devices is demonstrated for the first time. Extension-gate overlap, active dopant concentration and distribution inside extensions and epi source/drain are observed with 1 nm-spatial resolution along X, Y and Z-directions. Using this new technique providing full 3D-carrier mapping we analyzed different processing flows for sub-10nm fin width FinFETs, identified possible failure mechanisms, and demonstrated the direct link between improved performance and 3D-carrier distribution at the nm-scale.