Pub Date : 2015-12-07DOI: 10.1109/IEDM.2015.7409742
M. Duan, J. F. Zhang, A. Manut, Z. Ji, W. Zhang, A. Asenov, L. Gerrer, D. Reid, H. Razaidi, D. Vigar, V. Chandra, R. Aitken, B. Kaczer, G. Groeseneken
As CMOS scales down, hot carrier aging (HCA) scales up and can be a limiting aging process again. This has motivated re-visiting HCA, but recent works have focused on accelerated HCA by raising stress biases and there is little information on HCA under use-biases. Early works proposed that HCA mechanism under high and low biases are different, questioning if the high-bias data can be used for predicting HCA under use-bias. A key advance of this work is proposing a new methodology for evaluating the HCA-induced variation under use-bias. For the first time, the capability of predicting HCA under use-bias is experimentally verified. The importance of separating RTN from HCA is demonstrated. We point out the HCA measured by the commercial Source-Measure-Unit (SMU) gives erroneous power exponent. The proposed methodology minimizes the number of tests and the model requires only 3 fitting parameters, making it readily implementable.
{"title":"Hot carrier aging and its variation under use-bias: Kinetics, prediction, impact on Vdd and SRAM","authors":"M. Duan, J. F. Zhang, A. Manut, Z. Ji, W. Zhang, A. Asenov, L. Gerrer, D. Reid, H. Razaidi, D. Vigar, V. Chandra, R. Aitken, B. Kaczer, G. Groeseneken","doi":"10.1109/IEDM.2015.7409742","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409742","url":null,"abstract":"As CMOS scales down, hot carrier aging (HCA) scales up and can be a limiting aging process again. This has motivated re-visiting HCA, but recent works have focused on accelerated HCA by raising stress biases and there is little information on HCA under use-biases. Early works proposed that HCA mechanism under high and low biases are different, questioning if the high-bias data can be used for predicting HCA under use-bias. A key advance of this work is proposing a new methodology for evaluating the HCA-induced variation under use-bias. For the first time, the capability of predicting HCA under use-bias is experimentally verified. The importance of separating RTN from HCA is demonstrated. We point out the HCA measured by the commercial Source-Measure-Unit (SMU) gives erroneous power exponent. The proposed methodology minimizes the number of tests and the model requires only 3 fitting parameters, making it readily implementable.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130634812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-07DOI: 10.1109/IEDM.2015.7409717
G. Piccolboni, G. Molas, J. Portal, R. Coquand, M. Bocquet, D. Garbin, E. Vianello, C. Carabasse, V. Delaye, C. Pellissier, T. Magis, C. Cagli, M. Gely, O. Cueto, D. Deleruyelle, G. Ghibaudo, B. De Salvo, L. Perniola
Combining Resistive RAM concept with Vertical NAND technology and design, Vertical RRAM (VRRAM) was recently proposed as a cost-effective and extensible technology for future mass data storage applications [1]. 3D RRAM based neural networks were also proposed to emulate the potentiation and depression of a synapse [2], but more complex circuits were not discussed. In previous works [3-4], various RRAM based neuromorphic circuits were proposed and investigated, using planar devices.
{"title":"Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications","authors":"G. Piccolboni, G. Molas, J. Portal, R. Coquand, M. Bocquet, D. Garbin, E. Vianello, C. Carabasse, V. Delaye, C. Pellissier, T. Magis, C. Cagli, M. Gely, O. Cueto, D. Deleruyelle, G. Ghibaudo, B. De Salvo, L. Perniola","doi":"10.1109/IEDM.2015.7409717","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409717","url":null,"abstract":"Combining Resistive RAM concept with Vertical NAND technology and design, Vertical RRAM (VRRAM) was recently proposed as a cost-effective and extensible technology for future mass data storage applications [1]. 3D RRAM based neural networks were also proposed to emulate the potentiation and depression of a synapse [2], but more complex circuits were not discussed. In previous works [3-4], various RRAM based neuromorphic circuits were proposed and investigated, using planar devices.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129679198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409810
Wenjie Lu, Jin K. Kim, J. Klem, S. Hawkins, J. D. del Alamo
We demonstrate the first InGaSb p-channel FinFET. Towards this goal, we have developed a fin dry-etch technology which yields fins as narrow as 15 nm with vertical sidewalls, an aspect ratio greater than 10 and low sidewall interface state density. We have also realized Si-compatible ohmic contacts with ultra-low contact resistivity of 3.5-10-8 Q-cm2. InGaSb FinFETs with fin widths down to 30 nm and gate lengths down to 100 nm have been fabricated. The Al2O3 gate oxide has an EOT of 1.8 nm. A high gm of 122 μS/μm is obtained in devices of Wf = 100 nm and Lg = 100 nm. In the smallest devices with Wf = 30 nm and Lg = 100 nm, a gm of 78 μS/μm is achieved.
{"title":"An InGaSb p-channel FinFET","authors":"Wenjie Lu, Jin K. Kim, J. Klem, S. Hawkins, J. D. del Alamo","doi":"10.1109/IEDM.2015.7409810","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409810","url":null,"abstract":"We demonstrate the first InGaSb p-channel FinFET. Towards this goal, we have developed a fin dry-etch technology which yields fins as narrow as 15 nm with vertical sidewalls, an aspect ratio greater than 10 and low sidewall interface state density. We have also realized Si-compatible ohmic contacts with ultra-low contact resistivity of 3.5-10-8 Q-cm2. InGaSb FinFETs with fin widths down to 30 nm and gate lengths down to 100 nm have been fabricated. The Al2O3 gate oxide has an EOT of 1.8 nm. A high gm of 122 μS/μm is obtained in devices of Wf = 100 nm and Lg = 100 nm. In the smallest devices with Wf = 30 nm and Lg = 100 nm, a gm of 78 μS/μm is achieved.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":" 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120829746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409626
C. Gamrat, O. Bichler, David Roclin
Since the rapid development of post-CMOS technologies in the last decade, there has been a growing interest in utilizing them for implementing neuromorphic or brain-like computing machines. Besides attempts to build realistic circuits that would mimic the functioning of biological neurons as close as possible [1][2], our team is focused on implementing neuromorphic circuits suitable for embedded applications. This objective puts the emphasis on two majors concerns: integration and energy efficiency. In our quest for ultimate integration, we first report on investigating for the best synapse-like technology among the realm of potential candidates. We then report our investigations on the feasibility of large crossbars of synapse-like devices and show that there is still a long way ahead. Finally in an effort to tackle the energy problem, we introduce spike based coding for deep neuromorphic architectures and discuss our argument that spike coding combined with memristive synaptic devices could pave the way for future embedded neuromorphic circuits.
{"title":"Memristive based device arrays combined with Spike based coding can enable efficient implementations of embedded neuromorphic circuits","authors":"C. Gamrat, O. Bichler, David Roclin","doi":"10.1109/IEDM.2015.7409626","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409626","url":null,"abstract":"Since the rapid development of post-CMOS technologies in the last decade, there has been a growing interest in utilizing them for implementing neuromorphic or brain-like computing machines. Besides attempts to build realistic circuits that would mimic the functioning of biological neurons as close as possible [1][2], our team is focused on implementing neuromorphic circuits suitable for embedded applications. This objective puts the emphasis on two majors concerns: integration and energy efficiency. In our quest for ultimate integration, we first report on investigating for the best synapse-like technology among the realm of potential candidates. We then report our investigations on the feasibility of large crossbars of synapse-like devices and show that there is still a long way ahead. Finally in an effort to tackle the energy problem, we introduce spike based coding for deep neuromorphic architectures and discuss our argument that spike coding combined with memristive synaptic devices could pave the way for future embedded neuromorphic circuits.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122625564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409623
G. Indiveri, Federico Corradi, Ning Qiao
We present a full custom hardware implementation of a deep neural network, built using multiple neuromorphic VLSI devices that integrate analog neuron and synapse circuits together with digital asynchronous logic circuits. The deep network comprises an event-based convolutional stage for feature extraction connected to a spike-based learning stage for feature classification. We describe the properties of the chips used to implement the network and present preliminary experimental results that validate the approach proposed.
{"title":"Neuromorphic architectures for spiking deep neural networks","authors":"G. Indiveri, Federico Corradi, Ning Qiao","doi":"10.1109/IEDM.2015.7409623","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409623","url":null,"abstract":"We present a full custom hardware implementation of a deep neural network, built using multiple neuromorphic VLSI devices that integrate analog neuron and synapse circuits together with digital asynchronous logic circuits. The deep network comprises an event-based convolutional stage for feature extraction connected to a spike-based learning stage for feature classification. We describe the properties of the chips used to implement the network and present preliminary experimental results that validate the approach proposed.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114497113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409785
P. B. Pillai, M. M. De Souza
We demonstrate high performance ZnO TFTs with record field effect mobility 229 cm2/V.s, on/off ratio exceeding 107 (limited only by our simple device structure) and sub threshold swing (S) <;150 mV/dec, surpassing the performance of many reported amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors.1,2 The tail state distribution of the density of states (DOS) in ZnO extracted via 2D numerical simulations matched to experiment, demonstrates unequivocally a similar mobility mechanism that underpins all Transparent Conducting Oxides (TCOs)-whether amorphous or not. The characteristic Temperature of ZnO is found to be ~463 K and the tail state density of states (DOS) is ~1.3 ×1020cm-3eV-1.
{"title":"Transport mechanism in sub 100°C processed high mobility polycrystalline ZnO transparent thin film transistors","authors":"P. B. Pillai, M. M. De Souza","doi":"10.1109/IEDM.2015.7409785","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409785","url":null,"abstract":"We demonstrate high performance ZnO TFTs with record field effect mobility 229 cm2/V.s, on/off ratio exceeding 107 (limited only by our simple device structure) and sub threshold swing (S) <;150 mV/dec, surpassing the performance of many reported amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors.1,2 The tail state distribution of the density of states (DOS) in ZnO extracted via 2D numerical simulations matched to experiment, demonstrates unequivocally a similar mobility mechanism that underpins all Transparent Conducting Oxides (TCOs)-whether amorphous or not. The characteristic Temperature of ZnO is found to be ~463 K and the tail state density of states (DOS) is ~1.3 ×1020cm-3eV-1.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122109681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409765
Tsung-Ta Wu, C. Shen, J. Shieh, Wen-Hsien Huang, Hsing-Hsiang Wang, F. Hsueh, Hisu-Chih Chen, Chih-Chao Yang, Tung-Ying Hsieh, Bo-Yuan Chen, Y. Shiao, Chao-Shun Yang, G. Huang, Kai-Shin Li, T. Hsueh, Chien-Fu Chen, Wei-Hao Chen, Fu-Liang Yang, Meng-Fan Chang, W. Yeh
For the first time, a CO2 far-infrared laser annealing (CO2-FIR-LA) technology was developed as the activation solution to enable highly heterogeneous integration without causing device degradation for TSV-free monolithic 3DIC. This process is capable to implement small-area-small-load vertical connectors, gate-first high-k/metal gate MOSFETs and non-Al metal inter-connects. Such a far-infrared laser annealing exhibits excellent selective activation capability that enables performance-enhanced stacked sub-40nm UTB-MOSFETs (Ion-enhanced over 50 %). Unlike TSV-based 3D-IC, this 3D Monolithic IC enables ultra-wide-IO connections between layers to achieve high bandwidth with less power consumption. A test chip with logic circuits, 6T SRAM, ReRAM, sense amplifiers, analog amplifiers and gas sensors was integrated to confirm the superiority in heterogeneous integration of proposed CO2-FIR-LA technology. This chip demonstrates the most variable functions above reported 3D Monolithic ICs. This CO2-FIR-LA based TSV-free 3D Monolithic IC can realize low cost, small footprint, and highly heterogeneous integration for Internet of Things.
首次开发了CO2远红外激光退火(CO2- fir - la)技术作为激活解决方案，实现了无tsv单片3DIC的高度异质集成，而不会导致器件退化。该工艺能够实现小面积小负载垂直连接器，栅极优先高k/金属栅极mosfet和非al金属互连。这种远红外激光退火具有出色的选择性激活能力，可以实现性能增强的40nm以下utb - mosfet堆叠(离子增强超过50%)。与基于tsv的3D-IC不同，这种3D单片IC可以在层之间实现超宽io连接，以更低的功耗实现高带宽。集成了逻辑电路、6T SRAM、ReRAM、感测放大器、模拟放大器和气体传感器的测试芯片，证实了所提出的CO2-FIR-LA技术在异构集成方面的优势。该芯片展示了上述报道的3D单片集成电路中最可变的功能。该基于CO2-FIR-LA的无tsv 3D单片集成电路可实现物联网低成本、小占地、高异构集成。
{"title":"Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things","authors":"Tsung-Ta Wu, C. Shen, J. Shieh, Wen-Hsien Huang, Hsing-Hsiang Wang, F. Hsueh, Hisu-Chih Chen, Chih-Chao Yang, Tung-Ying Hsieh, Bo-Yuan Chen, Y. Shiao, Chao-Shun Yang, G. Huang, Kai-Shin Li, T. Hsueh, Chien-Fu Chen, Wei-Hao Chen, Fu-Liang Yang, Meng-Fan Chang, W. Yeh","doi":"10.1109/IEDM.2015.7409765","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409765","url":null,"abstract":"For the first time, a CO2 far-infrared laser annealing (CO2-FIR-LA) technology was developed as the activation solution to enable highly heterogeneous integration without causing device degradation for TSV-free monolithic 3DIC. This process is capable to implement small-area-small-load vertical connectors, gate-first high-k/metal gate MOSFETs and non-Al metal inter-connects. Such a far-infrared laser annealing exhibits excellent selective activation capability that enables performance-enhanced stacked sub-40nm UTB-MOSFETs (Ion-enhanced over 50 %). Unlike TSV-based 3D-IC, this 3D Monolithic IC enables ultra-wide-IO connections between layers to achieve high bandwidth with less power consumption. A test chip with logic circuits, 6T SRAM, ReRAM, sense amplifiers, analog amplifiers and gas sensors was integrated to confirm the superiority in heterogeneous integration of proposed CO2-FIR-LA technology. This chip demonstrates the most variable functions above reported 3D Monolithic ICs. This CO2-FIR-LA based TSV-free 3D Monolithic IC can realize low cost, small footprint, and highly heterogeneous integration for Internet of Things.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122128716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409620
H. Cheng, W. Chien, M. BrightSky, Y. Ho, Y. Zhu, A. Ray, R. Bruce, W. Kim, C. Yeh, H. Lung, C. Lam
Attempts to improve the retention so far must sacrifice switching speed. This work explores new phase change material based on pseudobinary GaSb-Ge system. The resulting new phase-change material has demonstrated fast switching speed of 80 ns, long endurance of 1G cycles and excellent data retention that survives 250°C-300 hrs. The 10 years-220°C data retention is the best ever reported. It is also the fastest material that can pass the solder bonding criteria for embedded automotive applications.
{"title":"Novel fast-switching and high-data retention phase-change memory based on new Ga-Sb-Ge material","authors":"H. Cheng, W. Chien, M. BrightSky, Y. Ho, Y. Zhu, A. Ray, R. Bruce, W. Kim, C. Yeh, H. Lung, C. Lam","doi":"10.1109/IEDM.2015.7409620","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409620","url":null,"abstract":"Attempts to improve the retention so far must sacrifice switching speed. This work explores new phase change material based on pseudobinary GaSb-Ge system. The resulting new phase-change material has demonstrated fast switching speed of 80 ns, long endurance of 1G cycles and excellent data retention that survives 250°C-300 hrs. The 10 years-220°C data retention is the best ever reported. It is also the fastest material that can pass the solder bonding criteria for embedded automotive applications.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117005573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409684
Jiang Cao, D. Logoteta, Sibel Ozkaya, B. Biel, A. Cresti, M. Pala, D. Esseni
We propose a model Hamiltonian for van der Waals tunnel transistors relying on a few physical parameters that we calibrate against DFT band structure calculations. This approach allowed us to develop a fully three-dimensional (3-D) NEGF based simulator and to investigate fundamental and design aspects related to van der Waals tunnel transistors, such as: (a) area and edge tunneling components, and scaling with device area; (b) impact of top gate alignment and back-oxide thickness on the device performance; (c) influence of inelastic phonon scattering on the device operation and sub-threshold swing; (d) benchmarking of switching energy and delay.
{"title":"A computational study of van der Waals tunnel transistors: Fundamental aspects and design challenges","authors":"Jiang Cao, D. Logoteta, Sibel Ozkaya, B. Biel, A. Cresti, M. Pala, D. Esseni","doi":"10.1109/IEDM.2015.7409684","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409684","url":null,"abstract":"We propose a model Hamiltonian for van der Waals tunnel transistors relying on a few physical parameters that we calibrate against DFT band structure calculations. This approach allowed us to develop a fully three-dimensional (3-D) NEGF based simulator and to investigate fundamental and design aspects related to van der Waals tunnel transistors, such as: (a) area and edge tunneling components, and scaling with device area; (b) impact of top gate alignment and back-oxide thickness on the device performance; (c) influence of inelastic phonon scattering on the device operation and sub-threshold swing; (d) benchmarking of switching energy and delay.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"6 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129737657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-01DOI: 10.1109/IEDM.2015.7409719
M. Prezioso, I. Kataeva, F. Merrikh-Bayat, B. Hoskins, G. Adam, T. Sota, K. Likharev, D. Strukov
Neuromorphic pattern classifiers were implemented, for the first time, using transistor-free integrated crossbar circuits with bilayer metal-oxide memristors. 10×6- and 10×8-crosspoint neuromorphic networks were trained in-situ using a Manhattan-Rule algorithm to separate a set of 3×3 binary images: into 3 classes using the batch-mode training, and into 4 classes using the stochastic-mode training, respectively. Simulation of much larger, multilayer neural network classifiers based on such technology has sown that their fidelity may be on a par with the state-of-the-art results for software-implemented networks.
{"title":"Modeling and implementation of firing-rate neuromorphic-network classifiers with bilayer Pt/Al2O3/TiO2−x/Pt Memristors","authors":"M. Prezioso, I. Kataeva, F. Merrikh-Bayat, B. Hoskins, G. Adam, T. Sota, K. Likharev, D. Strukov","doi":"10.1109/IEDM.2015.7409719","DOIUrl":"https://doi.org/10.1109/IEDM.2015.7409719","url":null,"abstract":"Neuromorphic pattern classifiers were implemented, for the first time, using transistor-free integrated crossbar circuits with bilayer metal-oxide memristors. 10×6- and 10×8-crosspoint neuromorphic networks were trained in-situ using a Manhattan-Rule algorithm to separate a set of 3×3 binary images: into 3 classes using the batch-mode training, and into 4 classes using the stochastic-mode training, respectively. Simulation of much larger, multilayer neural network classifiers based on such technology has sown that their fidelity may be on a par with the state-of-the-art results for software-implemented networks.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"26 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130615576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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