A control constrained test scheduling approach for VLSI circuits

Abstract

One of the major objectives of research in VLSI circuit testing is to minimise the testing time and the associated overhead for test control. Sophisticated test scheduling algorithms have been proposed previously to reduce test application time. However, the cost of test control which constitutes a major part of the total test overhead has not received due attention. The authors propose a control constrained test scheduling approach. The cost of test control is evaluated based on the test controller hardware and the cost of test control signal distribution network. An algorithm has been designed to generate a schedule that minimises the combined cost of test application time and test control.<>