Techniques for reducing hardware requirement of self checking combinational circuits

S. Pagey, S. Sherlekar, G. Venkatesh
{"title":"Techniques for reducing hardware requirement of self checking combinational circuits","authors":"S. Pagey, S. Sherlekar, G. Venkatesh","doi":"10.1109/ATS.1992.224419","DOIUrl":null,"url":null,"abstract":"The authors present two methods that can be used to reduce the hardware requirement for a self checking implementation of a given combinational function. They give examples to show that these give very significant reduction over the traditional SFS implementation. They believe that by careful use of such optimizations, the size of self checking implementations can be brought down within acceptable limits for use in practice.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"324 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings First Asian Test Symposium (ATS `92)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1992.224419","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

The authors present two methods that can be used to reduce the hardware requirement for a self checking implementation of a given combinational function. They give examples to show that these give very significant reduction over the traditional SFS implementation. They believe that by careful use of such optimizations, the size of self checking implementations can be brought down within acceptable limits for use in practice.<>
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降低组合电路自检硬件要求的技术
作者提出了两种方法,可用于减少对给定组合函数的自检实现的硬件要求。他们给出的例子表明,与传统的SFS实现相比,这些方法显著降低了能耗。他们认为,通过仔细使用这种优化,可以将自检实现的大小降低到可接受的范围内,以便在实践中使用。
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Localization and aftereffect of automatic test generation A practical approach for the diagnosis of a MIMD network A complement-based fast algorithm to generate universal test sets for combinational function blocks A control constrained test scheduling approach for VLSI circuits Techniques for reducing hardware requirement of self checking combinational circuits
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