The authors present a classification of bridging faults in ISCAS combinational circuits and analyze the L/sub DDQ/ testability of this sort of faults. A procedure for test pattern generation is implemented and it is applied to these circuits. The problem of testing feedback bridging faults is also analyzed showing that this type of fault is also testable by I/sub DDQ/ even if they exhibit an oscillating behaviour. This result is verified through simulated and experimental data.<>
{"title":"Quiescent current testing of combinational circuits with bridging faults","authors":"M. Roca, A. Rubio","doi":"10.1109/ATS.1992.224437","DOIUrl":"https://doi.org/10.1109/ATS.1992.224437","url":null,"abstract":"The authors present a classification of bridging faults in ISCAS combinational circuits and analyze the L/sub DDQ/ testability of this sort of faults. A procedure for test pattern generation is implemented and it is applied to these circuits. The problem of testing feedback bridging faults is also analyzed showing that this type of fault is also testable by I/sub DDQ/ even if they exhibit an oscillating behaviour. This result is verified through simulated and experimental data.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116807296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors propose a method of diagnosing any logical fault in combinational circuits. The basic idea of the method has been obtained from an observation that only an error generated on one of the fault-nets propagates often to the primary outputs under a given test though more than one fault-net exist in the circuit under test. In this method, the fault-nets are located through a repetition of deducing candidates for each individual fault-net under the assumption of single fault-net and ascertaining which is the real one by probing. Probing internal nets is done only for finding the real fault-nets from these candidates. Consequently, it becomes possible to greatly decrease the number of probed nets. Preliminary experimental results show that fault locations are almost completely identified by probing 20% of the nets at most.<>
{"title":"A method of diagnosing logical faults in combinational circuits","authors":"K. Yamazaki, T. Yamada","doi":"10.1109/ATS.1992.224413","DOIUrl":"https://doi.org/10.1109/ATS.1992.224413","url":null,"abstract":"The authors propose a method of diagnosing any logical fault in combinational circuits. The basic idea of the method has been obtained from an observation that only an error generated on one of the fault-nets propagates often to the primary outputs under a given test though more than one fault-net exist in the circuit under test. In this method, the fault-nets are located through a repetition of deducing candidates for each individual fault-net under the assumption of single fault-net and ascertaining which is the real one by probing. Probing internal nets is done only for finding the real fault-nets from these candidates. Consequently, it becomes possible to greatly decrease the number of probed nets. Preliminary experimental results show that fault locations are almost completely identified by probing 20% of the nets at most.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126960734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A sufficient condition under which a minimum verification test set (MVTS) for a combinational circuit has 2/sup w/ elements is derived, where w is the maximum number of inputs on which any output depends, and an algorithm to find an NVTS with 2/sup w/ elements for any CUT with up to four outputs is described.<>
{"title":"Minimum verification test set for combinational circuit","authors":"H. Michinishi, T. Yokohira, T. Okamoto","doi":"10.1109/ATS.1992.224428","DOIUrl":"https://doi.org/10.1109/ATS.1992.224428","url":null,"abstract":"A sufficient condition under which a minimum verification test set (MVTS) for a combinational circuit has 2/sup w/ elements is derived, where w is the maximum number of inputs on which any output depends, and an algorithm to find an NVTS with 2/sup w/ elements for any CUT with up to four outputs is described.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126670525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As complexity of circuits has increased and design techniques have evolved, testing them has evolved as well. This evolution has led to take into account high-level behavioral descriptions of circuits for generating their test patterns. The authors explain the reasons which have motivated research laboratory to become interested in behavioral generation. Having surveyed the representative work of the domain, the authors present their approach for generating test patterns from high-level behavioral descriptions.<>
{"title":"Automatic behavioral test pattern generation for digital circuits","authors":"A. Courbis, J. Santucci, N. Giambiasi","doi":"10.1109/ATS.1992.224447","DOIUrl":"https://doi.org/10.1109/ATS.1992.224447","url":null,"abstract":"As complexity of circuits has increased and design techniques have evolved, testing them has evolved as well. This evolution has led to take into account high-level behavioral descriptions of circuits for generating their test patterns. The authors explain the reasons which have motivated research laboratory to become interested in behavioral generation. Having surveyed the representative work of the domain, the authors present their approach for generating test patterns from high-level behavioral descriptions.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124029484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new procedure for the synthesis of easily testable PLA-based finite state machines is presented. All combinational irredundant crosspoint faults in the PLA implementing the combinational component of the machine are testable. The machines produced have short machine-independent justification sequences for each state. The maximum length of these sequences is nv. A unit length sequence verifies that the machine has been actually placed in the reset state after the application of the reset input. The authors have developed an algorithm which does not use fault simulation. Combinational fault simulation is introduced in order to reduce the number of test vectors needed. There is an area overhead associated to the increment in testability. These area penalties have been shown to be smaller for larger machines. The scheme reduces the area overhead of similar approaches previously reported.<>
{"title":"Synthesis for testability of PLA based finite state machines","authors":"M. Avedillo, J. Quintana, J. L. Huertas","doi":"10.1109/ATS.1992.224409","DOIUrl":"https://doi.org/10.1109/ATS.1992.224409","url":null,"abstract":"A new procedure for the synthesis of easily testable PLA-based finite state machines is presented. All combinational irredundant crosspoint faults in the PLA implementing the combinational component of the machine are testable. The machines produced have short machine-independent justification sequences for each state. The maximum length of these sequences is nv. A unit length sequence verifies that the machine has been actually placed in the reset state after the application of the reset input. The authors have developed an algorithm which does not use fault simulation. Combinational fault simulation is introduced in order to reduce the number of test vectors needed. There is an area overhead associated to the increment in testability. These area penalties have been shown to be smaller for larger machines. The scheme reduces the area overhead of similar approaches previously reported.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126557856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors investigate methods for reducing the time to test the suspected faulty units in a real-time system. They provide a clue to the tester about possible faulty locations within each unit. Hence only a fraction of the resources within a unit need to be tested. This is accomplished by keeping track of the resources used, called the hardware utilization vector (HUV), when a program is executing. The authors demonstrate the average reduction in test time of cache and memory subsystems and improvement in meeting deadlines under the presence of faults.<>
{"title":"On reducing test time and meeting deadlines in real-time systems","authors":"T. R. Sarnaik, Arun Kumar Somani","doi":"10.1109/ATS.1992.224416","DOIUrl":"https://doi.org/10.1109/ATS.1992.224416","url":null,"abstract":"The authors investigate methods for reducing the time to test the suspected faulty units in a real-time system. They provide a clue to the tester about possible faulty locations within each unit. Hence only a fraction of the resources within a unit need to be tested. This is accomplished by keeping track of the resources used, called the hardware utilization vector (HUV), when a program is executing. The authors demonstrate the average reduction in test time of cache and memory subsystems and improvement in meeting deadlines under the presence of faults.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133159992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An efficient parallel pattern multiple-fault propagation (MFP) technique for the single stuck-at fault simulation in combinational circuits is presented. This technique is able to operate in conjunction with several existing fault simulation techniques, such as the parallel-pattern simulation and the fanout-free region concept. Experimental results have shown significant improvements in the simulation speed over the existing approaches. The fault simulator described adopts different simulation algorithms at different simulation stages to optimize the simulator performance.<>
{"title":"Accelerated fault simulation utilizing multiple-fault propagation","authors":"Y. Xing, G. van Brakel, H. Kerkhoff","doi":"10.1109/ATS.1992.224432","DOIUrl":"https://doi.org/10.1109/ATS.1992.224432","url":null,"abstract":"An efficient parallel pattern multiple-fault propagation (MFP) technique for the single stuck-at fault simulation in combinational circuits is presented. This technique is able to operate in conjunction with several existing fault simulation techniques, such as the parallel-pattern simulation and the fanout-free region concept. Experimental results have shown significant improvements in the simulation speed over the existing approaches. The fault simulator described adopts different simulation algorithms at different simulation stages to optimize the simulator performance.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116907404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Hagihara, C. Ohkubo, F. Okamoto, H. Yamada, M. Takada, T. Enomoto
The authors describe design for testability (DFT) techniques implemented in a 200 MFLOPS 64-bit floating point vector-pipelined processor (VPP) ULSI. Scan tests were implemented into the central control unit (CCU), as well as into the input/output buffers, which are served by a boundary scan (BS) chain. Newly developed random pattern built-in self tests (BISTs) were implemented into the register file (RF), as well as into two arithmetic units (ADD/SFT and MPY/DIV/LU). Fault coverage for the RF (2-port SRAMs) was 100%. Average fault coverage for pipelined arithmetic units, achieved by a BIST with approximately 1,000,000(2/sup 20/) random patterns, was 98%. Combination of scan test and BIST-internal partial scan-achieves a partial-scan test of the arithmetic units and 99.6% fault coverage for the MPY/DIV/LU.<>
{"title":"Design for testability in a 200 MFLOPS vector-pipelined processor (VPP)-ULSI","authors":"Y. Hagihara, C. Ohkubo, F. Okamoto, H. Yamada, M. Takada, T. Enomoto","doi":"10.1109/ATS.1992.224404","DOIUrl":"https://doi.org/10.1109/ATS.1992.224404","url":null,"abstract":"The authors describe design for testability (DFT) techniques implemented in a 200 MFLOPS 64-bit floating point vector-pipelined processor (VPP) ULSI. Scan tests were implemented into the central control unit (CCU), as well as into the input/output buffers, which are served by a boundary scan (BS) chain. Newly developed random pattern built-in self tests (BISTs) were implemented into the register file (RF), as well as into two arithmetic units (ADD/SFT and MPY/DIV/LU). Fault coverage for the RF (2-port SRAMs) was 100%. Average fault coverage for pipelined arithmetic units, achieved by a BIST with approximately 1,000,000(2/sup 20/) random patterns, was 98%. Combination of scan test and BIST-internal partial scan-achieves a partial-scan test of the arithmetic units and 99.6% fault coverage for the MPY/DIV/LU.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117079631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micropipelines, suggested by Ivan Sutherland (1989) form an elegant scheme for asynchronous implementation of pipelined circuits. The authors analyse the faulty behavior of micropipelines and propose schemes for testing. They suggest that the control part of the micropipeline is concurrently testable during normal operation and that test pattern generation for the data part logic can be reduced to that for combinational circuits, with a simple modification only in the test application method. Testing latches require a two-pattern test which can be generated using test pattern generation techniques for combinational circuits.<>
Ivan Sutherland(1989)提出的微管道形成了异步实现流水线电路的优雅方案。对微管道的故障行为进行了分析，并提出了检测方案。他们认为，微管道的控制部分在正常运行时可以同时进行测试，数据部分逻辑的测试模式生成可以简化为组合电路的测试模式生成，只需在测试应用方法中进行简单的修改。测试锁存器需要双模式测试，可以使用组合电路的测试模式生成技术生成。
{"title":"Issues in fault modelling and testing of micropipelines","authors":"S. Pagey, S. Sherlekar, G. Venkatesh","doi":"10.1109/ATS.1992.224446","DOIUrl":"https://doi.org/10.1109/ATS.1992.224446","url":null,"abstract":"Micropipelines, suggested by Ivan Sutherland (1989) form an elegant scheme for asynchronous implementation of pipelined circuits. The authors analyse the faulty behavior of micropipelines and propose schemes for testing. They suggest that the control part of the micropipeline is concurrently testable during normal operation and that test pattern generation for the data part logic can be reduced to that for combinational circuits, with a simple modification only in the test application method. Testing latches require a two-pattern test which can be generated using test pattern generation techniques for combinational circuits.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"10 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132258407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors have laid the foundations for a functional test generation procedure based on a cyclomatic complexity measure (CCM) and on the reduced, ordered binary decision diagram representation (ROBDD) for Boolean function manipulation. The CCM has been defined for one-output and multi-output electronic circuits predicting a minimal number of test vectors. This new test generation approach, called Cyclogen, has been implemented, and the tests for several functional primitives as well as for the ISCAS-85 benchmark circuits have been generated successfully. The results show that this approach is effective and promising.<>
{"title":"Cyclogen: automatic, functional-level test generator","authors":"B. Ayari, B. Kaminska","doi":"10.1109/ATS.1992.224449","DOIUrl":"https://doi.org/10.1109/ATS.1992.224449","url":null,"abstract":"The authors have laid the foundations for a functional test generation procedure based on a cyclomatic complexity measure (CCM) and on the reduced, ordered binary decision diagram representation (ROBDD) for Boolean function manipulation. The CCM has been defined for one-output and multi-output electronic circuits predicting a minimal number of test vectors. This new test generation approach, called Cyclogen, has been implemented, and the tests for several functional primitives as well as for the ISCAS-85 benchmark circuits have been generated successfully. The results show that this approach is effective and promising.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130292610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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