S. Ehrich, R. Bertenburg, M. Agethen, A. Brennemann, W. Brockerhoff, F. Tegude
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引用次数: 1
Abstract
For simulation of digital circuits realized in Direct Coupled FET Logic (DCFL) using depletion-type as well as enhancement-type Heterostructure-Field Effect Transistors (HFET) a consistent model that is able to describe both types of transistors is necessary. The developed analytical PSPICE model takes into account all relevant intrinsic and parasitic effects. This model can be used for dc- as well as rf-simulations and is scaleable with respect to gate-width as well as gate-length.
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