Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193189
S. Smith, A. Walton, S. Bond, A. Ross, J. Stevenson, A. Gundlach
Focused Ion Beam (FIB) systems are commonly used to image, repair and modify integrated circuits by cutting holes in passivation to create vias or to selectively break metal tracks. The ion beam can also be used to deposit a metal, such as platinum, to create new connections. These techniques are very useful tools for debugging designs and testing possible changes to the circuit without the expense of new mask sets or silicon. This paper presents test structures to characterise a FIB platinum deposition process. Sheet resistance test structures have been fabricated using a FIB tool and the results of testing these structures are presented. This data will enable resistors with a known value to be fabricated in addition to conducting straps.
{"title":"Test structures for the electrical characterisation of platinum deposited by focused ion beam","authors":"S. Smith, A. Walton, S. Bond, A. Ross, J. Stevenson, A. Gundlach","doi":"10.1109/ICMTS.2002.1193189","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193189","url":null,"abstract":"Focused Ion Beam (FIB) systems are commonly used to image, repair and modify integrated circuits by cutting holes in passivation to create vias or to selectively break metal tracks. The ion beam can also be used to deposit a metal, such as platinum, to create new connections. These techniques are very useful tools for debugging designs and testing possible changes to the circuit without the expense of new mask sets or silicon. This paper presents test structures to characterise a FIB platinum deposition process. Sheet resistance test structures have been fabricated using a FIB tool and the results of testing these structures are presented. This data will enable resistors with a known value to be fabricated in addition to conducting straps.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125399901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193177
D. Szmyd, L. Gambus, A. Wilbanks
RF coupling of signals between circuit blocks can be severe. We quantify electrical isolation on concentric test structures using s-parameter measurements up to 50 GHz. The use of deep trenches greatly improves isolation. Guard rings and junction isolation are also beneficial.
{"title":"Strategies and test structures for improving isolation between circuit blocks","authors":"D. Szmyd, L. Gambus, A. Wilbanks","doi":"10.1109/ICMTS.2002.1193177","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193177","url":null,"abstract":"RF coupling of signals between circuit blocks can be severe. We quantify electrical isolation on concentric test structures using s-parameter measurements up to 50 GHz. The use of deep trenches greatly improves isolation. Guard rings and junction isolation are also beneficial.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130502768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193168
W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella, B. Majoux, V. Chowdhury
We present in this paper a new characterization method dedicated to an analog low consumption application design. A test structure, based on a bandgap reference voltage, that allows parameters extraction at the circuit operating point, is presented. This test structure is used to adjust the final SPICE parameters in order to calibrate the electrical measurement value of each component of the circuit on the chip. An improvement of the design is simulated, tested and validated on silicon.
{"title":"Low current application dedicated process characterization method","authors":"W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella, B. Majoux, V. Chowdhury","doi":"10.1109/ICMTS.2002.1193168","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193168","url":null,"abstract":"We present in this paper a new characterization method dedicated to an analog low consumption application design. A test structure, based on a bandgap reference voltage, that allows parameters extraction at the circuit operating point, is presented. This test structure is used to adjust the final SPICE parameters in order to calibrate the electrical measurement value of each component of the circuit on the chip. An improvement of the design is simulated, tested and validated on silicon.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120963805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193170
Y. Shimizu, Mitsuo Nakamura, T. Matsuoka, Kenji Taniguchi
A new test structure consisting of an MOSFET array and peripheral decoder circuits is proposed to study statistical variation (mismatch) in MOSFETs' characteristics. Kelvin technique was implemented in the structure to cancel parasitic resistance of metal wiring and transmission gates in such a way that any MOSFET in the array can be measured at the same bias condition. Accurate electrical measurements using the structure makes it possible to derive statistical variation of threshold voltage and transconductance of MOSFETs placed in small area.
{"title":"Test structure for precise statistical characteristics measurement of MOSFETs","authors":"Y. Shimizu, Mitsuo Nakamura, T. Matsuoka, Kenji Taniguchi","doi":"10.1109/ICMTS.2002.1193170","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193170","url":null,"abstract":"A new test structure consisting of an MOSFET array and peripheral decoder circuits is proposed to study statistical variation (mismatch) in MOSFETs' characteristics. Kelvin technique was implemented in the structure to cancel parasitic resistance of metal wiring and transmission gates in such a way that any MOSFET in the array can be measured at the same bias condition. Accurate electrical measurements using the structure makes it possible to derive statistical variation of threshold voltage and transconductance of MOSFETs placed in small area.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126475195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193203
R. Difrenza, P. Llinares, S. Taupin, R. Palla, C. Garnier, G. Ghibaudo
This paper compares the random local fluctuations, commonly known under the term of mismatch, with the variations that appear at the wafer level for the MOS transistor and the polysilicon resistor. In particular, it highlights the strong decrease of MOSFET matching performance when the device area is reduced, by comparison to the fluctuations at the wafer level. This amazing tendency involves that the well-known phenomenon responsible for the MOS transistor mismatch do not dominate for the smallest devices. In particular, the impact of polysilicon edge roughness induced by stochastic process during photolithography or etching is investigated.
{"title":"Comparison between matching parameters and fluctuations at the wafer level","authors":"R. Difrenza, P. Llinares, S. Taupin, R. Palla, C. Garnier, G. Ghibaudo","doi":"10.1109/ICMTS.2002.1193203","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193203","url":null,"abstract":"This paper compares the random local fluctuations, commonly known under the term of mismatch, with the variations that appear at the wafer level for the MOS transistor and the polysilicon resistor. In particular, it highlights the strong decrease of MOSFET matching performance when the device area is reduced, by comparison to the fluctuations at the wafer level. This amazing tendency involves that the well-known phenomenon responsible for the MOS transistor mismatch do not dominate for the smallest devices. In particular, the impact of polysilicon edge roughness induced by stochastic process during photolithography or etching is investigated.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127420873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193183
C. McAndrew
This paper presents three useful numerical techniques for compact modeling. First, a new approach to modeling non-uniform vertical doping profiles in MOSFETs is presented, based on non-linear mapping of the backgate bias. Second, a technique that guarantees that limiting of V/sub ds/ at saturation will not lead to glitches in output conductance is presented. Finally, requirements for limiting functions for V/sub ds/ that do not cause discontinuities in high order derivatives at V/sub ds/ = 0 are defined. Examples of limiting functions that maintain proper symmetry are given. The techniques to eliminate glitches in output conductance and maintain symmetry are applicable to MOSFET and resistor models.
{"title":"Useful numerical techniques for compact modeling","authors":"C. McAndrew","doi":"10.1109/ICMTS.2002.1193183","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193183","url":null,"abstract":"This paper presents three useful numerical techniques for compact modeling. First, a new approach to modeling non-uniform vertical doping profiles in MOSFETs is presented, based on non-linear mapping of the backgate bias. Second, a technique that guarantees that limiting of V/sub ds/ at saturation will not lead to glitches in output conductance is presented. Finally, requirements for limiting functions for V/sub ds/ that do not cause discontinuities in high order derivatives at V/sub ds/ = 0 are defined. Examples of limiting functions that maintain proper symmetry are given. The techniques to eliminate glitches in output conductance and maintain symmetry are applicable to MOSFET and resistor models.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"1128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114305932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193195
Christopher Hess, B. Stine, L. Weiland, Kazuhiro Sawada
Manufacturing of integrated circuits relies on the sequence of many hundred process steps. Each of these steps will have more or less variation, which has to be within a,certain limit to guarantee the chips functionality at a target speed. But, not every chip layout is susceptive to process variation the same way, which requires a link between process,capabilities and product design. This paper will present a novel Logic Characterization Vehicle (LCV) to investigate the yield and performance impact of process variation on high volume product chips. The LCV combines and manipulates new or already documented circuits like memory cells and combinatorial logic circuits within a JIG interface that allows fast and easy testability. Beside the functionality of such circuits, also path delay as well as cross talk issues can be determined. A standard digital functional tester can be used, since all timing critical measurements will be performed within the JIG. The described method allows early implementation of existing circuits for future technology nodes (shrinks). A Design Of Experiments (DOE) based implementation of possible layout manipulations will determine their impact on yield and performance of a target design as well as its sensitivity to process variation. The described approach can be used at a much earlier stage of product and process development, which will significantly shorten yield ramp.
{"title":"Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits","authors":"Christopher Hess, B. Stine, L. Weiland, Kazuhiro Sawada","doi":"10.1109/ICMTS.2002.1193195","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193195","url":null,"abstract":"Manufacturing of integrated circuits relies on the sequence of many hundred process steps. Each of these steps will have more or less variation, which has to be within a,certain limit to guarantee the chips functionality at a target speed. But, not every chip layout is susceptive to process variation the same way, which requires a link between process,capabilities and product design. This paper will present a novel Logic Characterization Vehicle (LCV) to investigate the yield and performance impact of process variation on high volume product chips. The LCV combines and manipulates new or already documented circuits like memory cells and combinatorial logic circuits within a JIG interface that allows fast and easy testability. Beside the functionality of such circuits, also path delay as well as cross talk issues can be determined. A standard digital functional tester can be used, since all timing critical measurements will be performed within the JIG. The described method allows early implementation of existing circuits for future technology nodes (shrinks). A Design Of Experiments (DOE) based implementation of possible layout manipulations will determine their impact on yield and performance of a target design as well as its sensitivity to process variation. The described approach can be used at a much earlier stage of product and process development, which will significantly shorten yield ramp.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114796676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193185
T. Fan, T. Lu, S. Pan
Tunnel oxide quality is a key parameter during flash memory development. A high quality tunnel oxide will result in good cell endurance characteristics. However, the conventional tunnel oxide characterization is usually based on a large area capacitor test structure with a high sheet resistance floating poly-silicon gate, and, as a result, an over-estimated oxide quality is obtained. In this study, we design a new test structure and a new characterization methodology for tunnel oxide measurement. It is found that more accurate and reliable tunnel oxide lifetime prediction can be obtained with this new approach. Besides, this measurement is correlated to flash memory endurance performance.
{"title":"New spider-webs test structure and characterization methodology for flash memory tunnel oxide quality","authors":"T. Fan, T. Lu, S. Pan","doi":"10.1109/ICMTS.2002.1193185","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193185","url":null,"abstract":"Tunnel oxide quality is a key parameter during flash memory development. A high quality tunnel oxide will result in good cell endurance characteristics. However, the conventional tunnel oxide characterization is usually based on a large area capacitor test structure with a high sheet resistance floating poly-silicon gate, and, as a result, an over-estimated oxide quality is obtained. In this study, we design a new test structure and a new characterization methodology for tunnel oxide measurement. It is found that more accurate and reliable tunnel oxide lifetime prediction can be obtained with this new approach. Besides, this measurement is correlated to flash memory endurance performance.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129956801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193186
D. McCarthy, M. O’Shea, R. Duane, K. McCarthy, A. Concannon, A. Mathewson
A novel measurement technique utilising a new test structure is applied to the existing subthreshold methodology to extract coupling coefficients of the Top-Floating-Gate (TFG) cell. The TFG cell is unique in structure and operation in comparison with current NVM devices. It is designed with the FG surrounding the CG which greatly enhances the gate coupling ratio (/spl alpha//sub cg/) allowing a small area cell and avoiding the use of expensive z-direction extensions unlike the industry standard stacked-gate approach. This work quantifies this benefit for the area efficient TFG cell design.
{"title":"Extraction of the coupling coefficients for the top-floating-gate (TFG) flash EEPROM cell","authors":"D. McCarthy, M. O’Shea, R. Duane, K. McCarthy, A. Concannon, A. Mathewson","doi":"10.1109/ICMTS.2002.1193186","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193186","url":null,"abstract":"A novel measurement technique utilising a new test structure is applied to the existing subthreshold methodology to extract coupling coefficients of the Top-Floating-Gate (TFG) cell. The TFG cell is unique in structure and operation in comparison with current NVM devices. It is designed with the FG surrounding the CG which greatly enhances the gate coupling ratio (/spl alpha//sub cg/) allowing a small area cell and avoiding the use of expensive z-direction extensions unlike the industry standard stacked-gate approach. This work quantifies this benefit for the area efficient TFG cell design.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122381254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-04-08DOI: 10.1109/ICMTS.2002.1193174
F. Ingvarson, M. Linder, K. Jeppson
A straightforward method for extracting the base and emitter resistances is presented. The method has the following properties: 1) only a standard forward Gummel measurement on one transistor is required, 2) current-crowding and conductivity-modulation in the base are accounted for through the use of an accurate base resistance model, and 3) the resistance parameters are extracted using a non-linear optimization step. Furthermore, a technique for extraction of the high-injection parameters of a modified collector current model is also presented.
{"title":"Extraction of the base and emitter resistances in bipolar transistors using an accurate base resistance model","authors":"F. Ingvarson, M. Linder, K. Jeppson","doi":"10.1109/ICMTS.2002.1193174","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193174","url":null,"abstract":"A straightforward method for extracting the base and emitter resistances is presented. The method has the following properties: 1) only a standard forward Gummel measurement on one transistor is required, 2) current-crowding and conductivity-modulation in the base are accounted for through the use of an accurate base resistance model, and 3) the resistance parameters are extracted using a non-linear optimization step. Furthermore, a technique for extraction of the high-injection parameters of a modified collector current model is also presented.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130863082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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