C. Jeng, W. K. Wan, H.H. Lin, M. Liang, K. Tang, I. Kao, H. Lo, K. Chi, T.C. Huang, C. Yao, C. Lin, M. D. Lei, C. Hsia, M. Liang
{"title":"BEOL process integration of 65nm Cu/low k interconnects","authors":"C. Jeng, W. K. Wan, H.H. Lin, M. Liang, K. Tang, I. Kao, H. Lo, K. Chi, T.C. Huang, C. Yao, C. Lin, M. D. Lei, C. Hsia, M. Liang","doi":"10.1109/IITC.2004.1345745","DOIUrl":null,"url":null,"abstract":"The process development, characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the 65 nm CMOS technology node are presented. Significant modifications and improvements over 90nm node have been implemented to overcome those challenges as design rules shrink, which include top via corner rounding control for the robust EM/SM reliability, and inline e-beam inspection for via/trench processes optimization. An in-house developed ECP additive \"Trameca\" for good Cu gap filling and a controllable hump height for good CMP performance are adopted to achieve tight Rs distributions. The facts that 100% yields of 2.1 millions via chain structure and open/short free on 5m long comb/meander structures along with SM/EM meeting the spec all demonstrated the technology to be a highly manufacturable BEOL process for 65 nm technology node.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2004.1345745","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
The process development, characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the 65 nm CMOS technology node are presented. Significant modifications and improvements over 90nm node have been implemented to overcome those challenges as design rules shrink, which include top via corner rounding control for the robust EM/SM reliability, and inline e-beam inspection for via/trench processes optimization. An in-house developed ECP additive "Trameca" for good Cu gap filling and a controllable hump height for good CMP performance are adopted to achieve tight Rs distributions. The facts that 100% yields of 2.1 millions via chain structure and open/short free on 5m long comb/meander structures along with SM/EM meeting the spec all demonstrated the technology to be a highly manufacturable BEOL process for 65 nm technology node.
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