Pub Date : 2004-06-09DOI: 10.1109/IITC.2004.1345703
B. Dang, C. Patel, H. Thacker, M. Bakir, K. Martin, J. Meindl
Compliant interconnects can enable wafer level packages with high I/O density, high reliability and better performances with low cost and small size. A fabrication process for SoL compliant interconnects has been optimized to achieve high yield and compatibility with standard back-end-of-line (BEOL) as well as flip-chip bonding processes. The optimized fabrication process further enables a reliable joining between the IC and SoL compliant interconnects to the next level of packaging without the use of an expensive underfilling process.
{"title":"Optimal implementation of sea of leads (SoL) compliant interconnect technology","authors":"B. Dang, C. Patel, H. Thacker, M. Bakir, K. Martin, J. Meindl","doi":"10.1109/IITC.2004.1345703","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345703","url":null,"abstract":"Compliant interconnects can enable wafer level packages with high I/O density, high reliability and better performances with low cost and small size. A fabrication process for SoL compliant interconnects has been optimized to achieve high yield and compatibility with standard back-end-of-line (BEOL) as well as flip-chip bonding processes. The optimized fabrication process further enables a reliable joining between the IC and SoL compliant interconnects to the next level of packaging without the use of an expensive underfilling process.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129650233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-09DOI: 10.1109/IITC.2004.1345720
Girish Dixit, Lester A. D'Cruz, Sang-Wook Ahn, Yi Zheng, Josephine J. Chang, M. Naik, Alexandros T. Demos, D. Witty, Hichem M'Saad
A porous carbon doped oxide has been developed using a conventional PECVD reactor. Sequential electron beam treatment using a flood beam provides a means for removal of the thermally labile organic species and results in a porous material with high thermal stability. Film properties and integration results presented show the viability of integrating this film into a conventional dual damascene interconnect flow.
{"title":"Film properties and integration performance of a nano-porous carbon doped oxide","authors":"Girish Dixit, Lester A. D'Cruz, Sang-Wook Ahn, Yi Zheng, Josephine J. Chang, M. Naik, Alexandros T. Demos, D. Witty, Hichem M'Saad","doi":"10.1109/IITC.2004.1345720","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345720","url":null,"abstract":"A porous carbon doped oxide has been developed using a conventional PECVD reactor. Sequential electron beam treatment using a flood beam provides a means for removal of the thermally labile organic species and results in a porous material with high thermal stability. Film properties and integration results presented show the viability of integrating this film into a conventional dual damascene interconnect flow.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133429362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345740
E. Micler, Ching-Te Li, A. Krishnan, C. Jin, M. Jain
Organosilicate glass (OSG) deposited by plasma enhanced chemical vapour deposition (PECVD) is a likely candidate for 65nm node low k interconnect dielectric. Electron beam (e-beam) treatment efficiently stiffens porous PECVD OSG and may enable extension of PECVD OSG beyond the 65 nm node. Charge damage during e-beam exposure should be considered before implementing e-beam treatments for low k dielectrics. The effects of e-beam cathode potential on CMOS transistor threshold voltage and gate dielectric leakage current are investigated using 130nm node CMOS transistors. The impact of e-beam treatments was negligible on devices with 1.7nm gate dielectrics, but can adversely impact the 6.7nm dielectric devices.
{"title":"A charge damage study using an electron beam low k treatment","authors":"E. Micler, Ching-Te Li, A. Krishnan, C. Jin, M. Jain","doi":"10.1109/IITC.2004.1345740","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345740","url":null,"abstract":"Organosilicate glass (OSG) deposited by plasma enhanced chemical vapour deposition (PECVD) is a likely candidate for 65nm node low k interconnect dielectric. Electron beam (e-beam) treatment efficiently stiffens porous PECVD OSG and may enable extension of PECVD OSG beyond the 65 nm node. Charge damage during e-beam exposure should be considered before implementing e-beam treatments for low k dielectrics. The effects of e-beam cathode potential on CMOS transistor threshold voltage and gate dielectric leakage current are investigated using 130nm node CMOS transistors. The impact of e-beam treatments was negligible on devices with 1.7nm gate dielectrics, but can adversely impact the 6.7nm dielectric devices.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124818385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345683
K. Lee, H.J. Shin, J.W. Hwang, S.W. Nam, Y.J. Moon, Y. Wee, I.G. Kim, W. Park, J.H. Kim, S.J. Lee, K.K. Park, H. Kang, K. Suh
A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).
{"title":"Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node","authors":"K. Lee, H.J. Shin, J.W. Hwang, S.W. Nam, Y.J. Moon, Y. Wee, I.G. Kim, W. Park, J.H. Kim, S.J. Lee, K.K. Park, H. Kang, K. Suh","doi":"10.1109/IITC.2004.1345683","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345683","url":null,"abstract":"A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123754605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345682
A. Grill, D. Edelstein, D. Restaino, M. Lane, S. Gates, E. Liniger, T. Shaw, X. Liu, D. Klaus, V. Patel, S. Cohen, E. Simonyi, N. Klymko, S. Lane, K. Ida, S. Vogt, T. Van Kleeck, C. Davis, M. Ono, T. Nogami, T. Ivers
The research integration of SiCOH films in a reliable ULSI integrated circuit chip imposes many requirements on the properties of the dielectric material. This paper describes a selection and optimization process for choosing the best film to be integrated in Cu wiring levels of ULSI CMOS chips in the 90 nm technology node.
{"title":"Optimization of SiCOH dielectrics for integration in a 90nm CMOS technology","authors":"A. Grill, D. Edelstein, D. Restaino, M. Lane, S. Gates, E. Liniger, T. Shaw, X. Liu, D. Klaus, V. Patel, S. Cohen, E. Simonyi, N. Klymko, S. Lane, K. Ida, S. Vogt, T. Van Kleeck, C. Davis, M. Ono, T. Nogami, T. Ivers","doi":"10.1109/IITC.2004.1345682","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345682","url":null,"abstract":"The research integration of SiCOH films in a reliable ULSI integrated circuit chip imposes many requirements on the properties of the dielectric material. This paper describes a selection and optimization process for choosing the best film to be integrated in Cu wiring levels of ULSI CMOS chips in the 90 nm technology node.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122794607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345724
T. Dalton, N. Fuller, C. Tweedie, D. Dunn, C. Labelle, S. Gates, M. Colburn, S.T. Chen, T. Lai, R. Dellaguardia, K. Petrarca, C. Dziobkowski, K. Kumar, S. Siddiqui
Modification of low-k dielectric materials during photoresist plasma stripping was examined using a variety of analytical techniques. These techniques were initially applied to blanket wafers and were subsequently applied to both specially-designed test structures and product structures on patterned wafers. Results of these experiments are presented and analyzed.
{"title":"Ash-induced modification of porous and dense SiCOH inter-level-dielectric (ILD) materials during damascene plasma processing","authors":"T. Dalton, N. Fuller, C. Tweedie, D. Dunn, C. Labelle, S. Gates, M. Colburn, S.T. Chen, T. Lai, R. Dellaguardia, K. Petrarca, C. Dziobkowski, K. Kumar, S. Siddiqui","doi":"10.1109/IITC.2004.1345724","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345724","url":null,"abstract":"Modification of low-k dielectric materials during photoresist plasma stripping was examined using a variety of analytical techniques. These techniques were initially applied to blanket wafers and were subsequently applied to both specially-designed test structures and product structures on patterned wafers. Results of these experiments are presented and analyzed.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114141764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345710
Hoyeol Cho, P. Kapur, Krishna C. Saraswat
Power dissipation between electrical and optical interconnects for high-speed inter-chip communication is compared. A power minimization strategy for optical interconnects is developed and its scaling trends are shown. Optical interconnect when compared with the state-of-the-art electrical interconnect yields lower power beyond a critical length (43cm at 6Gb/s and 100nm technology node). The critical length is fully characterized as a function of system requirements (bit rate and bit-error rate) and interconnect's end-device parameters (detector capacitance, receiver sensitivity and offset). Higher bit rates yield lower critical lengths making optical interconnects more favorable in the future.
{"title":"Power comparison between high-speed electrical and optical interconnects for inter-chip communication","authors":"Hoyeol Cho, P. Kapur, Krishna C. Saraswat","doi":"10.1109/IITC.2004.1345710","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345710","url":null,"abstract":"Power dissipation between electrical and optical interconnects for high-speed inter-chip communication is compared. A power minimization strategy for optical interconnects is developed and its scaling trends are shown. Optical interconnect when compared with the state-of-the-art electrical interconnect yields lower power beyond a critical length (43cm at 6Gb/s and 100nm technology node). The critical length is fully characterized as a function of system requirements (bit rate and bit-error rate) and interconnect's end-device parameters (detector capacitance, receiver sensitivity and offset). Higher bit rates yield lower critical lengths making optical interconnects more favorable in the future.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123897593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345709
M. Saint-Laurent, M. Swaminathan
For long interconnects, the power-supply noise injected through the repeaters can be more critical than crosstalk simply because there is no easy way to get rid of it. This paper rigorously analyzes the injection mechanism using a novel device model. A closed-form expression quantifying the interconnect delay variations caused by the noise is derived. For typical 130-nm interconnects, the model is shown to be very accurate.
{"title":"A model for power-supply noise injection in long interconnects","authors":"M. Saint-Laurent, M. Swaminathan","doi":"10.1109/IITC.2004.1345709","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345709","url":null,"abstract":"For long interconnects, the power-supply noise injected through the repeaters can be more critical than crosstalk simply because there is no easy way to get rid of it. This paper rigorously analyzes the injection mechanism using a novel device model. A closed-form expression quantifying the interconnect delay variations caused by the noise is derived. For typical 130-nm interconnects, the model is shown to be very accurate.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123611845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345765
W. Woods, Y. Tretiakov, K. Vaed, D. Ahlgren, J. Rascoe, R. Singh
This paper presents a new on-chip transmission line interconnect structure which offers the potential of superior return and insertion loss characteristics compared to the equivalent standard transmission line device. Conventional on-chip coplanar waveguides (CPW) and differential pairs are routed in a single metal layer in the chip's metal-dielectric stack. The vertically stacked coplanar waveguide (PW) transmission lines presented here consist of metal lines on multiple metal levels connected by continuous via bars. The additional cross-sectional area of the VCPW topology decreases interconnect resistance while the increased effective device thickness increases capacitance to neighboring ground return lines leading to a characteristics impedance reduction.
{"title":"Vertically-stacked on-chip SiGe/BiCMOS/RFCMOS coplanar waveguides","authors":"W. Woods, Y. Tretiakov, K. Vaed, D. Ahlgren, J. Rascoe, R. Singh","doi":"10.1109/IITC.2004.1345765","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345765","url":null,"abstract":"This paper presents a new on-chip transmission line interconnect structure which offers the potential of superior return and insertion loss characteristics compared to the equivalent standard transmission line device. Conventional on-chip coplanar waveguides (CPW) and differential pairs are routed in a single metal layer in the chip's metal-dielectric stack. The vertically stacked coplanar waveguide (PW) transmission lines presented here consist of metal lines on multiple metal levels connected by continuous via bars. The additional cross-sectional area of the VCPW topology decreases interconnect resistance while the increased effective device thickness increases capacitance to neighboring ground return lines leading to a characteristics impedance reduction.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120961416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-07DOI: 10.1109/IITC.2004.1345674
T. Yoshie, K. Yoneda, N. Ohashi, N. Kobayashi
TDDB (time dependent dielectric breakdown) degradation mechanism of Cu damascene interconnects was investigated based on the results SiO/sub 2/ ILD. Cu diffusion can be analyzed by Ea(activation energy) variation of the leakage current. In the SiO/sub 2/ ILD, the lifetime is determined by Cu ion diffusion at the interface between diffusion barrier (DB) SiC and SiO/sub 2/ ILD. Cu diffusion induces Ea lowering of the leakage current, and it results in an increase of Poole-Frenkel and Schottky emission current through DB-SiC. On the other hand, the dielectric breakdown induced after a decrease in the leakage current in the porous-SiOC ILD. It is caused by the electric charge injection, not the Cu ion diffusion, at the interface on the porous-SiOC. It is important to form the rigid interface without any damage. Optimized DB-SiC process and hard mask SiO/sub 2/ protecting porous-SiOC improved the TDDB lifetime.
{"title":"TDDB degradation analysis using Ea of leakage current for reliable porous CVD SiOC(k=2.45)/Cu interconnects","authors":"T. Yoshie, K. Yoneda, N. Ohashi, N. Kobayashi","doi":"10.1109/IITC.2004.1345674","DOIUrl":"https://doi.org/10.1109/IITC.2004.1345674","url":null,"abstract":"TDDB (time dependent dielectric breakdown) degradation mechanism of Cu damascene interconnects was investigated based on the results SiO/sub 2/ ILD. Cu diffusion can be analyzed by Ea(activation energy) variation of the leakage current. In the SiO/sub 2/ ILD, the lifetime is determined by Cu ion diffusion at the interface between diffusion barrier (DB) SiC and SiO/sub 2/ ILD. Cu diffusion induces Ea lowering of the leakage current, and it results in an increase of Poole-Frenkel and Schottky emission current through DB-SiC. On the other hand, the dielectric breakdown induced after a decrease in the leakage current in the porous-SiOC ILD. It is caused by the electric charge injection, not the Cu ion diffusion, at the interface on the porous-SiOC. It is important to form the rigid interface without any damage. Optimized DB-SiC process and hard mask SiO/sub 2/ protecting porous-SiOC improved the TDDB lifetime.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126250396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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