Monolithic 3D Integrated BEOL Dual-Port Ferroelectric FET to Break the Tradeoff Between the Memory Window and the Ferroelectric Thickness

Abstract

In this work, we applied the dual-port concept to decouple the trade-off between the Ferroelectric (FE) thickness $(t_{FE})$ scaling and Memory Window (MW) in the amorphous channel ferroelectric FET (FeFET) for monolithic 3D BEOL integration. To prove the effectiveness of the proposed device structure and explore design space, we developed a fully cali-brated TCAD model and applied it to the amorphous channel FeFET study. We demonstrate the MW in two different scenarios: (i) write and read from the front gate, and (ii) write from the front gate and read from the back gate. We show the $t_{FE}$ and channel length scaling possibility in the second scenario, as well as the possibility for the multi-bit FeFET memory application.