Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118083
Harumi Seki, R. Ichihara, Y. Higashi, Y. Nakasaki, M. Saitoh, Masamichi Suzuki
The charge trapping characteristics in the silicon nitride (SiN) film were comprehensively studied by using dynamic CV technique with charge centroid analysis under various temperatures. We found two types of hole traps with short (long) time constant which capture holes at low (high) electric field. Traps with time constant down to 10 $mu mathrm{s}$ can be detected thanks to dynamic CV. For each kind of traps, the trapped charge density, spatial position, and the activation energy of de-trapping process are clarified, which are essential to understand the reliability issues of charge-trap memory devices.
{"title":"Comprehensive Analysis of Hole-Trapping in SiN Films with a Wide Range of Time Constants Based on Dynamic C-V","authors":"Harumi Seki, R. Ichihara, Y. Higashi, Y. Nakasaki, M. Saitoh, Masamichi Suzuki","doi":"10.1109/IRPS48203.2023.10118083","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118083","url":null,"abstract":"The charge trapping characteristics in the silicon nitride (SiN) film were comprehensively studied by using dynamic CV technique with charge centroid analysis under various temperatures. We found two types of hole traps with short (long) time constant which capture holes at low (high) electric field. Traps with time constant down to 10 $mu mathrm{s}$ can be detected thanks to dynamic CV. For each kind of traps, the trapped charge density, spatial position, and the activation energy of de-trapping process are clarified, which are essential to understand the reliability issues of charge-trap memory devices.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115474163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118095
I. Ji, A. Mathew, Jae-Hyung Park, Neal Oldham, Matthew McCain, S. Sabri, E. Brunt, B. Hull, D. Lichtenwalner, D. Gajewski, J. Palmour
For high power full SiC modules, the application requires highly reliable and robust 4H-SiC diodes in parallel with SiC MOSFETs. This work introduces new large size (50A rated) 1200V and 1700V 4H-SiC diodes which exhibit excellent performance under high temperature reverse bias (HTRB) and high voltage high temperature humidity (HV -H3TRB) conditions without sacrificing critical device performance such as forward voltage dropr $mathbf{(Vf)}$, Schottky Barrier height and ideality factor, and reverse leakage current. In this work, we have improved the device integration scheme for diode manufacturing, which enabled the successful completion of HTRB and HV-H3TRB qualification for automotive application.
{"title":"High Temperature and High Humidity Reliability Evaluation of Large-Area 1200V and 1700V SiC Diodes","authors":"I. Ji, A. Mathew, Jae-Hyung Park, Neal Oldham, Matthew McCain, S. Sabri, E. Brunt, B. Hull, D. Lichtenwalner, D. Gajewski, J. Palmour","doi":"10.1109/IRPS48203.2023.10118095","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118095","url":null,"abstract":"For high power full SiC modules, the application requires highly reliable and robust 4H-SiC diodes in parallel with SiC MOSFETs. This work introduces new large size (50A rated) 1200V and 1700V 4H-SiC diodes which exhibit excellent performance under high temperature reverse bias (HTRB) and high voltage high temperature humidity (HV -H3TRB) conditions without sacrificing critical device performance such as forward voltage dropr $mathbf{(Vf)}$, Schottky Barrier height and ideality factor, and reverse leakage current. In this work, we have improved the device integration scheme for diode manufacturing, which enabled the successful completion of HTRB and HV-H3TRB qualification for automotive application.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117047939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118207
Y. L. Yang, P. Tsao, C. W. Lin, Ross Lee, Olivia Ni, T. T. Chen, Y. Ting, C. Lai, Jason Yeh, Arnold Yang, Wayne Huang, Peng Chen, Charly Tsai, Ryan Yang, Y. S. Huang, B. Hsu, M. Z. Lee, T. Lee, Michael Huang, Coming Chen, L. Chu, H. Kao, N. S. Tsai
Near-zero defective parts per million (DPPM) and returned material authorization (RMA) from customers is the goal pursued by many companies. In this paper, a machine learning based method is proposed to detect outliers in the final test stage using the XGBoost algorithm and the Mahalanobis distance. We captured the weak integrated circuits (ICs) that passed the final test but failed in the system level test (SLT) or the verification of quality engineering aging (QEA). Compared to the random sampling, the experiments showed we could recognize 2x~3x weak IC ratio in the SLT and >10x in the QEA to achieve automotive grade DPPM.
{"title":"Performing Machine Learning Based Outlier Detection for Automotive Grade Products","authors":"Y. L. Yang, P. Tsao, C. W. Lin, Ross Lee, Olivia Ni, T. T. Chen, Y. Ting, C. Lai, Jason Yeh, Arnold Yang, Wayne Huang, Peng Chen, Charly Tsai, Ryan Yang, Y. S. Huang, B. Hsu, M. Z. Lee, T. Lee, Michael Huang, Coming Chen, L. Chu, H. Kao, N. S. Tsai","doi":"10.1109/IRPS48203.2023.10118207","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118207","url":null,"abstract":"Near-zero defective parts per million (DPPM) and returned material authorization (RMA) from customers is the goal pursued by many companies. In this paper, a machine learning based method is proposed to detect outliers in the final test stage using the XGBoost algorithm and the Mahalanobis distance. We captured the weak integrated circuits (ICs) that passed the final test but failed in the system level test (SLT) or the verification of quality engineering aging (QEA). Compared to the random sampling, the experiments showed we could recognize 2x~3x weak IC ratio in the SLT and >10x in the QEA to achieve automotive grade DPPM.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127181976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118115
N. J. Pieper, Y. Xiong, D. Ball, J. Pasternak, B. Bhuva
Single-port (SP) and two-port (TP) SRAM exposure to low-energy protons, alpha particles, and heavy-ions with varying supply voltages show particle linear energy transfer (LET) values and circuit design strongly influence charge collection, and subsequently SE cross-sections. Critical charge is not the dominant determinant of SE cross-section at the 5-nm node for all environments.
{"title":"Effects of Collected Charge and Drain Area on SE Response of SRAMs at the 5-nm FinFET Node","authors":"N. J. Pieper, Y. Xiong, D. Ball, J. Pasternak, B. Bhuva","doi":"10.1109/IRPS48203.2023.10118115","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118115","url":null,"abstract":"Single-port (SP) and two-port (TP) SRAM exposure to low-energy protons, alpha particles, and heavy-ions with varying supply voltages show particle linear energy transfer (LET) values and circuit design strongly influence charge collection, and subsequently SE cross-sections. Critical charge is not the dominant determinant of SE cross-section at the 5-nm node for all environments.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125838582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118026
D. Sangani, J. Diaz-Fortuny, E. Bury, B. Kaczer, G. Gielen
Shrinking reliability margins have created an increasing demand for circuit aging simulations, which enable product reliability assessment pre-production. Physical Design Kits (PDKs) of modern technologies have started to include compact models for transistor degradation mechanisms along with a dedicated reliability simulation framework. In this work, we present a study of the commercial aging models in a 28-nm CMOS technology from a designer perspective by comparison of the simulations with extensive measurement data at the device and the circuit level (ring oscillators). Moreover, using our custom table model compiled from our device-level measurement data, we model the BTI-driven component of circuit-level degradation and provide convincing evidence that mobility degradation due to NBTI plays an important role in the circuit aging phenomenon, thus emphasizing its need in SPICE-level NBTI models.
{"title":"The Role of Mobility Degradation in the BTI-Induced RO Aging in a 28-nm Bulk CMOS Technology: (Student paper)","authors":"D. Sangani, J. Diaz-Fortuny, E. Bury, B. Kaczer, G. Gielen","doi":"10.1109/IRPS48203.2023.10118026","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118026","url":null,"abstract":"Shrinking reliability margins have created an increasing demand for circuit aging simulations, which enable product reliability assessment pre-production. Physical Design Kits (PDKs) of modern technologies have started to include compact models for transistor degradation mechanisms along with a dedicated reliability simulation framework. In this work, we present a study of the commercial aging models in a 28-nm CMOS technology from a designer perspective by comparison of the simulations with extensive measurement data at the device and the circuit level (ring oscillators). Moreover, using our custom table model compiled from our device-level measurement data, we model the BTI-driven component of circuit-level degradation and provide convincing evidence that mobility degradation due to NBTI plays an important role in the circuit aging phenomenon, thus emphasizing its need in SPICE-level NBTI models.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126115425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118191
B. McGowan, M. Rakowski, Seungman Choi
Electromigration (EM) tests were performed on NiSi silicide heaters that are part of a photonic micro ring modulator (MRM). Measurement of the temperature kinetics of failure suggests an activation energy close to 2.0eV. Failure analyses confirm Ni migration is the failure mechanism. Reliability limits established by the EM tests combined with characterization of the MRM's temperature response quantifies the tradeoffs between device performance and reliability.
{"title":"Nickel Silicide Electromigration on Micro Ring Modulators for Silicon Photonics Technology","authors":"B. McGowan, M. Rakowski, Seungman Choi","doi":"10.1109/IRPS48203.2023.10118191","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118191","url":null,"abstract":"Electromigration (EM) tests were performed on NiSi silicide heaters that are part of a photonic micro ring modulator (MRM). Measurement of the temperature kinetics of failure suggests an activation energy close to 2.0eV. Failure analyses confirm Ni migration is the failure mechanism. Reliability limits established by the EM tests combined with characterization of the MRM's temperature response quantifies the tradeoffs between device performance and reliability.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"427 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115251987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117727
P. Lall, Ved Soni, Guneet Sethi, K. Yiang
Investigation of li-ion battery state of health (SOH) degradation and its modeling facilitates the determination of device warranty and can provide information about the device battery's health. For such studies, batteries undergo life-cycling tests with fixed cycling depths and charging currents (C-rates) across cycles, and the gathered degradation data is used for model development. However, in the real world, the cycling depth is generally not constant per cycle and varies across users. The SOH estimation of such use cases is challenging for lab-developed models. In this study, a semi-empirical SOH estimation regression model has been trained using fixed cycling depth and c-rate data and is validated using tests with randomized cycling depth and c-rate variation per cycle. Different upper and lower state of charge (SOC) limits were chosen to simulate different user profiles. Finally, multiple iterations of this model with different predictor variables have been tested to minimize the estimation error.
{"title":"Estimation of SOH Degradation of Coin Cells Subjected to Accelerated Life Cycling with Randomized Cycling Depths and C-Rates","authors":"P. Lall, Ved Soni, Guneet Sethi, K. Yiang","doi":"10.1109/IRPS48203.2023.10117727","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117727","url":null,"abstract":"Investigation of li-ion battery state of health (SOH) degradation and its modeling facilitates the determination of device warranty and can provide information about the device battery's health. For such studies, batteries undergo life-cycling tests with fixed cycling depths and charging currents (C-rates) across cycles, and the gathered degradation data is used for model development. However, in the real world, the cycling depth is generally not constant per cycle and varies across users. The SOH estimation of such use cases is challenging for lab-developed models. In this study, a semi-empirical SOH estimation regression model has been trained using fixed cycling depth and c-rate data and is validated using tests with randomized cycling depth and c-rate variation per cycle. Different upper and lower state of charge (SOC) limits were chosen to simulate different user profiles. Finally, multiple iterations of this model with different predictor variables have been tested to minimize the estimation error.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122869356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117671
H. Seo, T. Rim, Eunsun Lee, Sekyoung Jang, Kyosuk Chae, Jeonghoon Oh, H. Ban, Jooyoung Lee
The intermittent single-bit (SB) failure is one of the most important problems in DRAM technology development because it is almost impossible to reproduce and screen out. In this paper, the intermittent SB failure was analyzed theoretically. Based on our physical modeling, we suggested several technical methods to reduce the intermittent SB failure and got the experimental results that decrease the intermittent SB failure rate. Furthermore, we predicted the failure rate based on our theoretical model. The SB failure rate had over 85% consistency between prediction and results. Therefore, we proved that our failure modeling is appropriate for predicting the occurrence of the intermittent SB failure. Furthermore, we can propose the design of the next generation DRAM technology to achieve equivalent or better intermittent SB quality than the previous generation from the beginning of the development.
{"title":"Analysis of Intermittent Single-bit Failure on 10-nm node generation DRAM Devices","authors":"H. Seo, T. Rim, Eunsun Lee, Sekyoung Jang, Kyosuk Chae, Jeonghoon Oh, H. Ban, Jooyoung Lee","doi":"10.1109/IRPS48203.2023.10117671","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117671","url":null,"abstract":"The intermittent single-bit (SB) failure is one of the most important problems in DRAM technology development because it is almost impossible to reproduce and screen out. In this paper, the intermittent SB failure was analyzed theoretically. Based on our physical modeling, we suggested several technical methods to reduce the intermittent SB failure and got the experimental results that decrease the intermittent SB failure rate. Furthermore, we predicted the failure rate based on our theoretical model. The SB failure rate had over 85% consistency between prediction and results. Therefore, we proved that our failure modeling is appropriate for predicting the occurrence of the intermittent SB failure. Furthermore, we can propose the design of the next generation DRAM technology to achieve equivalent or better intermittent SB quality than the previous generation from the beginning of the development.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"08 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128204894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118190
Yuchong Wang, Siyuan Chen, Fanyu Liu, Bo Li, Jiangjiang Li, Yang Huang, Tiexin Zhang, Xu Zhang, Zhengsheng Han, T. Ye, J. Wan
The effects of $gamma$ radiation-induced positive trapped charges in the top buried oxide layer $boldsymbol{(mathrm{Q}_{text{BOX}1})}$ on the single event transient (SET) response of Double Silicon-On-Insulator (DSOI) transistors are examined for the first time through $gamma$ radiation and pulsed laser experiments. After $gamma$ radiation, a significant negative shift of threshold voltage for back-channel is observed for both DSOI NMOS and PMOS due to the $mathrm{Q}_{text{BO}mathrm{X}1}$. The SET current was measured at the device level, and the SET current peak and full width at half maximum (FWHM) were calculated. The impact of $boldsymbol{mathrm{Q}_{text{BOX}1}}$ and back-gate bias on the SET current of the DSOI devices are analyzed in detail. The experiments demonstrate that the SET current of NMOS is enhanced due to the parasitic bipolar transistor (PBT) effect activated by $boldsymbol{mathrm{Q}_{text{BOX}1}}$, which can be mitigated by applying a dynamic back-gate bias. However, the $boldsymbol{mathrm{Q}_{text{BOX}1}}$ inhibits the SET current and PBT for DSOI PMOS. TCAD simulations further validate this physical mechanism, and then the back-gate bias strategy is proposed for DSOI devices and circuits.
{"title":"The Effects of $gamma$ Radiation-Induced Trapped Charges on Single Event Transient in DSOI Technology","authors":"Yuchong Wang, Siyuan Chen, Fanyu Liu, Bo Li, Jiangjiang Li, Yang Huang, Tiexin Zhang, Xu Zhang, Zhengsheng Han, T. Ye, J. Wan","doi":"10.1109/IRPS48203.2023.10118190","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118190","url":null,"abstract":"The effects of $gamma$ radiation-induced positive trapped charges in the top buried oxide layer $boldsymbol{(mathrm{Q}_{text{BOX}1})}$ on the single event transient (SET) response of Double Silicon-On-Insulator (DSOI) transistors are examined for the first time through $gamma$ radiation and pulsed laser experiments. After $gamma$ radiation, a significant negative shift of threshold voltage for back-channel is observed for both DSOI NMOS and PMOS due to the $mathrm{Q}_{text{BO}mathrm{X}1}$. The SET current was measured at the device level, and the SET current peak and full width at half maximum (FWHM) were calculated. The impact of $boldsymbol{mathrm{Q}_{text{BOX}1}}$ and back-gate bias on the SET current of the DSOI devices are analyzed in detail. The experiments demonstrate that the SET current of NMOS is enhanced due to the parasitic bipolar transistor (PBT) effect activated by $boldsymbol{mathrm{Q}_{text{BOX}1}}$, which can be mitigated by applying a dynamic back-gate bias. However, the $boldsymbol{mathrm{Q}_{text{BOX}1}}$ inhibits the SET current and PBT for DSOI PMOS. TCAD simulations further validate this physical mechanism, and then the back-gate bias strategy is proposed for DSOI devices and circuits.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130350404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118128
R. Parker, J. Velamala, K. Shen, David Johnston, Yao-Feng Chang, S. Ramey, Siang-jhih Sean Wu, P. Penmatsa
Physical Unclonable Functions (PUFs) are low-cost cryptographic primitives used to generate unique, secure, and stable IDs for device authentication and secure communication. PUFs rely on process variation inherent in the manufacturing flow making it impossible to predict or clone chip IDs providing a high level of security and tamper resistance. A commonly studied PUF is the memory PUF which suffers high Bit Error Rate (BER) across environmental conditions. This paper introduces a novel NFET PUF featuring a Hot Carrier Injection (HCI) stress mechanism to lower BER to near zero. Post-Si data from a lkb PUF array fabricated in Intel4 FinFET technology is presented in comparison to a hybrid-SRAM style PUF. BER results were studied with different stress parameters enabling manufacturing flow for HCI based PUFs.
{"title":"A Physical Unclonable Function Leveraging Hot Carrier Injection Aging","authors":"R. Parker, J. Velamala, K. Shen, David Johnston, Yao-Feng Chang, S. Ramey, Siang-jhih Sean Wu, P. Penmatsa","doi":"10.1109/IRPS48203.2023.10118128","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118128","url":null,"abstract":"Physical Unclonable Functions (PUFs) are low-cost cryptographic primitives used to generate unique, secure, and stable IDs for device authentication and secure communication. PUFs rely on process variation inherent in the manufacturing flow making it impossible to predict or clone chip IDs providing a high level of security and tamper resistance. A commonly studied PUF is the memory PUF which suffers high Bit Error Rate (BER) across environmental conditions. This paper introduces a novel NFET PUF featuring a Hot Carrier Injection (HCI) stress mechanism to lower BER to near zero. Post-Si data from a lkb PUF array fabricated in Intel4 FinFET technology is presented in comparison to a hybrid-SRAM style PUF. BER results were studied with different stress parameters enabling manufacturing flow for HCI based PUFs.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130357529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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