A novel test structure to study intrinsic reliability of barrier/low-k

L. Zhao, Z. Tokei, Gianni Giai Gischia, M. Pantouvaki, K. Croes, G. Beyer
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引用次数: 18

Abstract

A novel test structure to study intrinsic reliability of barrier/low-k is proposed. The structure is based on a planar capacitor design where low-k film is deposited after the patterning of the capacitor, followed by metallization and Cu CMP. This so called low-k planar capacitor structure provides several unique capabilities to study various aspects of barrier/low-k TDDB compared with the conventional damascene structures. Two of the unique capabilities are presented in this paper. First, TDDB from a damage-free low-k material has been measured for the first time using the low-k planar capacitor structure. Second, the test structure is sensitive enough to quantify the impact of selected process conditions, such as barrier re-sputter and plasma treatments, on TDDB.
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一种研究势垒/低k固有可靠性的新型测试结构
提出了一种研究势垒/低k固有可靠性的新型测试结构。该结构基于平面电容器设计,在电容器图案化后沉积低钾薄膜,然后进行金属化和Cu CMP。与传统的damascene结构相比,这种所谓的低k平面电容器结构提供了几个独特的能力来研究势垒/低k TDDB的各个方面。本文介绍了其中两种独特的功能。首先,使用低k平面电容器结构首次测量了无损伤低k材料的TDDB。其次,测试结构足够敏感,可以量化所选工艺条件(如屏障再溅射和等离子体处理)对TDDB的影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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