Change in resistance of interconnect traces on flexible substrates is dependent on material properties and mechanical stress imposed by tensile strain. Dedicated test structures and a mechanical flexing / data collection system were designed and fabricated to collect time to failure data based on cyclic loading to different radii of curvature. We propose a life-stress model based on an inverse power law relationship defining the characteristic life of a Weibull life distribution.
{"title":"Life-stress relationship for thin film transistor gate line interconnects on flexible substrates","authors":"T. Martin, A. Christou","doi":"10.1117/12.840044","DOIUrl":"https://doi.org/10.1117/12.840044","url":null,"abstract":"Change in resistance of interconnect traces on flexible substrates is dependent on material properties and mechanical stress imposed by tensile strain. Dedicated test structures and a mechanical flexing / data collection system were designed and fabricated to collect time to failure data based on cyclic loading to different radii of curvature. We propose a life-stress model based on an inverse power law relationship defining the characteristic life of a Weibull life distribution.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131459409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173280
S. Fukatsu, I. Hirano, K. Tatsumura, Akiko Masada, S. Fujii, Y. Mitani, M. Goto, S. Inumiya, K. Nakajima, S. Kawanaka, T. Aoyama
We investigated bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB) in TaCx/HfSiON MOSFETs in terms of the effects of TaCx metal gate electrode, using various Ta composition and TaCx thickness. We find a dual nature of TaCx metal gate electrode effects on the reliability. The gate electrode has both positive and negative influence on BTI and TDDB. Though various TaCx layers were deposited on the same HfSiON layer, high composition of Ta in the TaCx layer and thick TaCx layer improve BTI and mobility, while they deteriorate time to breakdown (Tbd) because of the effects of metal gate induced defects.
{"title":"Dual nature of metal gate electrode effects on BTI and dielectric breakdown in TaC/HfSiON MISFETs","authors":"S. Fukatsu, I. Hirano, K. Tatsumura, Akiko Masada, S. Fujii, Y. Mitani, M. Goto, S. Inumiya, K. Nakajima, S. Kawanaka, T. Aoyama","doi":"10.1109/IRPS.2009.5173280","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173280","url":null,"abstract":"We investigated bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB) in TaCx/HfSiON MOSFETs in terms of the effects of TaCx metal gate electrode, using various Ta composition and TaCx thickness. We find a dual nature of TaCx metal gate electrode effects on the reliability. The gate electrode has both positive and negative influence on BTI and TDDB. Though various TaCx layers were deposited on the same HfSiON layer, high composition of Ta in the TaCx layer and thick TaCx layer improve BTI and mobility, while they deteriorate time to breakdown (Tbd) because of the effects of metal gate induced defects.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"s1-9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127197709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173388
M. H. Lee, S. T. Chang, S. Weng, W.H. Liu, K.-J. Chen, K. Ho, M. Liao, J.-J. Huang, G. Hu
The disordered bonds may generate a redistribution of trap states, resulting in unstable electrical characteristics such as threshold voltage, subthreshold swing, and mobility of carriers. The weak or broken bonds may contribute to the redistribution of trap states, and lead to unstable electrical characteristics of the a-Si:H TFTs on plastic substrates. We conclude that the DOS of an a-Si:H layer under mechanical strain is the fundamental reliability issue for the development of flexible electronics.
{"title":"The correlation between trap states and mechanical reliability of amorphous Si:H TFTs for flexible electronics","authors":"M. H. Lee, S. T. Chang, S. Weng, W.H. Liu, K.-J. Chen, K. Ho, M. Liao, J.-J. Huang, G. Hu","doi":"10.1109/IRPS.2009.5173388","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173388","url":null,"abstract":"The disordered bonds may generate a redistribution of trap states, resulting in unstable electrical characteristics such as threshold voltage, subthreshold swing, and mobility of carriers. The weak or broken bonds may contribute to the redistribution of trap states, and lead to unstable electrical characteristics of the a-Si:H TFTs on plastic substrates. We conclude that the DOS of an a-Si:H layer under mechanical strain is the fundamental reliability issue for the development of flexible electronics.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124788583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173228
P. Chakraborty, A. Appaswamy, P. Saha, N. K. Jha, J. Cressler, H. Yasuda, B. Eklund, R. Wise
An investigation of the high-voltage/high-current mixed-mode (M-M) stress-induced damage mechanisms of pnp silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) is presented. Different accelerated stress methods, including mixed-mode stress, reverse emitter-base (EB) stress, and forward collector plus reverse EB stress, were applied to pnp SiGe HBTs from a state-of-the-art complementary-SiGe BiCMOS process technology platform. The operative damage mechanism from the M-M stress method is identified. Experimental evidence of collector current change due to the M-M stress, and the experimental proof of the type of hot carriers (electrons vs. holes) responsible for the observed M-M stress damage are presented.
{"title":"Mixed-mode stress degradation mechanisms in pnp SiGe HBTs","authors":"P. Chakraborty, A. Appaswamy, P. Saha, N. K. Jha, J. Cressler, H. Yasuda, B. Eklund, R. Wise","doi":"10.1109/IRPS.2009.5173228","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173228","url":null,"abstract":"An investigation of the high-voltage/high-current mixed-mode (M-M) stress-induced damage mechanisms of pnp silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) is presented. Different accelerated stress methods, including mixed-mode stress, reverse emitter-base (EB) stress, and forward collector plus reverse EB stress, were applied to pnp SiGe HBTs from a state-of-the-art complementary-SiGe BiCMOS process technology platform. The operative damage mechanism from the M-M stress method is identified. Experimental evidence of collector current change due to the M-M stress, and the experimental proof of the type of hot carriers (electrons vs. holes) responsible for the observed M-M stress damage are presented.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123406115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173378
Lei Jiang, D. Pantuso, P. Sverdrup, W. Shih
The array of thermal modeling tools demonstrated here provided a new methodology to improve design and reliability evaluations as we tackle the power-thermal issues with current IC design. Net-specific Tj and interconnect SH prediction, when applied on large megablock designs, lead to significant thermal margins and benefit for electromigration. The analysis here also highlighted challenges associated with device and interconnect scaling, especially the small-scale thermal interaction and power density increases. Global-local CAD approaches and research into nano-scale heat transfer are critical in making sure that future design can make efficient use of the silicon scaling that is afforded by Moore's law, as we enter the new era of scaling for energy-efficient processors [8].
{"title":"Critical thermal issues in nanoscale IC design","authors":"Lei Jiang, D. Pantuso, P. Sverdrup, W. Shih","doi":"10.1109/IRPS.2009.5173378","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173378","url":null,"abstract":"The array of thermal modeling tools demonstrated here provided a new methodology to improve design and reliability evaluations as we tackle the power-thermal issues with current IC design. Net-specific Tj and interconnect SH prediction, when applied on large megablock designs, lead to significant thermal margins and benefit for electromigration. The analysis here also highlighted challenges associated with device and interconnect scaling, especially the small-scale thermal interaction and power density increases. Global-local CAD approaches and research into nano-scale heat transfer are critical in making sure that future design can make efficient use of the silicon scaling that is afforded by Moore's law, as we enter the new era of scaling for energy-efficient processors [8].","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"265 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123782761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173241
Minhua Lu, D. Shih, C. Goldsmith, T. Wassick
Two commonly used Pb-free solders, SnAg and SnCu, are studied for electromigration (EM) reliability. Two major EM failure mechanisms are identified in Sn-based Pb-free solders, which is mainly due to the differences in microstructures and Sn-grain orientation. In general, the EM damage in SnCu solder is driven by the fast interstitial diffusion of Ni and Cu away from solder/UBM interface and leads to early fails; while the damage in SnAg solders is mostly dominated by Sn-self diffusion resulting in longer lifetime. The effective activation energy is 0.95 eV for SnAg solder and 0.54 eV for SnCu solder. The current density power law exponent is 2 for SnAg and 1.2 for SnCu, respectively. Blech effect is observed in the solders with Sn-self diffusion dominated failures. The roles of Ag and Cu on EM performance will be discussed.
{"title":"Comparison of electromigration behaviors of SnAg and SnCu solders","authors":"Minhua Lu, D. Shih, C. Goldsmith, T. Wassick","doi":"10.1109/IRPS.2009.5173241","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173241","url":null,"abstract":"Two commonly used Pb-free solders, SnAg and SnCu, are studied for electromigration (EM) reliability. Two major EM failure mechanisms are identified in Sn-based Pb-free solders, which is mainly due to the differences in microstructures and Sn-grain orientation. In general, the EM damage in SnCu solder is driven by the fast interstitial diffusion of Ni and Cu away from solder/UBM interface and leads to early fails; while the damage in SnAg solders is mostly dominated by Sn-self diffusion resulting in longer lifetime. The effective activation energy is 0.95 eV for SnAg solder and 0.54 eV for SnCu solder. The current density power law exponent is 2 for SnAg and 1.2 for SnCu, respectively. Blech effect is observed in the solders with Sn-self diffusion dominated failures. The roles of Ag and Cu on EM performance will be discussed.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115563750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173250
M. C. casey, B. Bhuva, S.A. Nation, O. Amusan, T. D. Loveless, L. Massengill, M. C. casey, D. McMorrow, J. Melinger
Operating circuits in the subthreshold region is a simple method to lower total power consumption. The lower supply voltages decrease the electric fields present in the devices (resulting in lower charge collection), but increase the time required to remove the charge. These two competing mechanisms are characterized through two-photon absorption experiments for single-events to show that single-event vulnerability does not show a linear relationshiop with power supply voltage, as would be expected, in the subthreshold region. Single-event characterization is carried out using higher harmonic oscillation in ring oscillators with large numbers of stages over a wide range of supply voltages.
{"title":"Single-event effects on ultra-low power CMOS circuits","authors":"M. C. casey, B. Bhuva, S.A. Nation, O. Amusan, T. D. Loveless, L. Massengill, M. C. casey, D. McMorrow, J. Melinger","doi":"10.1109/IRPS.2009.5173250","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173250","url":null,"abstract":"Operating circuits in the subthreshold region is a simple method to lower total power consumption. The lower supply voltages decrease the electric fields present in the devices (resulting in lower charge collection), but increase the time required to remove the charge. These two competing mechanisms are characterized through two-photon absorption experiments for single-events to show that single-event vulnerability does not show a linear relationshiop with power supply voltage, as would be expected, in the subthreshold region. Single-event characterization is carried out using higher harmonic oscillation in ring oscillators with large numbers of stages over a wide range of supply voltages.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116070827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173366
R. Shaviv, S. Gopinath, M. Marshall, T. Mountsier, G. Dixit, Yu Jiang
The reliability of interconnects continues to be a formidable challenge as dimensions shrink from generation to generation. In this paper we demonstrate barrier/seed scaling, enabled by HCM® IONX PVD technology. We report high electromigration activation energy of ∼ 1 eV, and Jmax ≫ 6 MA/cm2, exceeding the ITRS 2007 requirements for the next several generations by a wide margin. Thinner barrier/seed with increased barrier etchback is shown to increase electromigration lifetime. Via stress migration results indicate that high barrier etchback is beneficial to reliability. TDDB results show a strong positive effect of barrier etchback on lifetime. We find that breakdown voltage for thinner barrier/seed is higher than that of the control. Breakdown voltage further increases with increased barrier etchback. For TDDB, the field acceleration coefficient, γ, improves with increased etch back from 4.3 (MV/cm)P−1 to 10 (MV/cm)−1 and the expected lifetime at operation conditions is improved by several orders of magnitude, exceeding requirements by a wide margin. This comprehensive study of PVD scalability proves a process space that provides the reliability margin necessary for continuing technology scaling for future generations.
{"title":"A comprehensive look at PVD scaling to meet the reliability requirements of advanced technology","authors":"R. Shaviv, S. Gopinath, M. Marshall, T. Mountsier, G. Dixit, Yu Jiang","doi":"10.1109/IRPS.2009.5173366","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173366","url":null,"abstract":"The reliability of interconnects continues to be a formidable challenge as dimensions shrink from generation to generation. In this paper we demonstrate barrier/seed scaling, enabled by HCM® IONX PVD technology. We report high electromigration activation energy of ∼ 1 eV, and Jmax ≫ 6 MA/cm2, exceeding the ITRS 2007 requirements for the next several generations by a wide margin. Thinner barrier/seed with increased barrier etchback is shown to increase electromigration lifetime. Via stress migration results indicate that high barrier etchback is beneficial to reliability. TDDB results show a strong positive effect of barrier etchback on lifetime. We find that breakdown voltage for thinner barrier/seed is higher than that of the control. Breakdown voltage further increases with increased barrier etchback. For TDDB, the field acceleration coefficient, γ, improves with increased etch back from 4.3 (MV/cm)P−1 to 10 (MV/cm)−1 and the expected lifetime at operation conditions is improved by several orders of magnitude, exceeding requirements by a wide margin. This comprehensive study of PVD scalability proves a process space that provides the reliability margin necessary for continuing technology scaling for future generations.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114447929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173343
Po-Yen Chiu, M. Ker, F. Tsai, Yeong-Jar Chang
A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.
{"title":"Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process","authors":"Po-Yen Chiu, M. Ker, F. Tsai, Yeong-Jar Chang","doi":"10.1109/IRPS.2009.5173343","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173343","url":null,"abstract":"A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128576028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173301
E. Cartier, A. Kerber
The stress-induced leakage current (SILC) in nFETs with SiO2/HfO2/TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage. It is shown that strong defect creation in the HfO2 causes a linear increase of the SILC with stress time. The SILC generation is found to be thermally activated with an activation energy, Ea ∼ 1 eV. In addition, the SILC formation exhibits a strong correlation with the threshold voltage (Vt) instability ΔIg/Ig ∼ dVt3. Both degradation phenomena show a strong hysteretic behavior with gate bias; the SILC and Vt-degradation are observed to be substantially reduced by applying a negative gate bias after stress. All these observations may be rationalized in terms of charge trapping in shallow HfO2 defects –such as oxygen vacancy – and by the generation of new shallow defects during stress. The defect generation process has a low activation energy, likely because of thin-film effects. Therefore, the SILC and the Vt instability are large under accelerated TDDB test conditions. It is also shown that the observed low activation energy in combination with the reversibility of the SILC has important implications for dielectric breakdown detection in dual-dielectric gate stacks.
{"title":"Stress-induced leakage current and defect generation in nFETs with HfO2/TiN gate stacks during positive-bias temperature stress","authors":"E. Cartier, A. Kerber","doi":"10.1109/IRPS.2009.5173301","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173301","url":null,"abstract":"The stress-induced leakage current (SILC) in nFETs with SiO<inf>2</inf>/HfO<inf>2</inf>/TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage. It is shown that strong defect creation in the HfO<inf>2</inf> causes a linear increase of the SILC with stress time. The SILC generation is found to be thermally activated with an activation energy, E<inf>a</inf> ∼ 1 eV. In addition, the SILC formation exhibits a strong correlation with the threshold voltage (V<inf>t</inf>) instability ΔI<inf>g</inf>/I<inf>g</inf> ∼ dV<inf>t</inf><sup>3</sup>. Both degradation phenomena show a strong hysteretic behavior with gate bias; the SILC and V<inf>t</inf>-degradation are observed to be substantially reduced by applying a negative gate bias after stress. All these observations may be rationalized in terms of charge trapping in shallow HfO<inf>2</inf> defects –such as oxygen vacancy – and by the generation of new shallow defects during stress. The defect generation process has a low activation energy, likely because of thin-film effects. Therefore, the SILC and the V<inf>t</inf> instability are large under accelerated TDDB test conditions. It is also shown that the observed low activation energy in combination with the reversibility of the SILC has important implications for dielectric breakdown detection in dual-dielectric gate stacks.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129434397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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