Gate-all-around CMOS (InAs n-FET and GaSb p-FET) based on vertically-stacked nanowires on a Si platform, enabled by extremely-thin buffer layer technology and common gate stack and contact modules

Abstract

We report the first demonstration of a novel vertically stacked structure comprising InAs nanowires and GaSb nanowires, enabled by an extremely-thin (sub-150 nm) III-V buffer technology on a Si platform. This led to the realization of InAs n-FETs and GaSb p-FETs based on the stacked InAs or GaSb nanowires (NWs), respectively, employing multiple common modules such as gate stack and contact processes. Decent transfer characteristics with SS of 126 mV/decade and DIBL of 285 mV/V were obtained for the InAs n-FET with a channel length LCH of 20 nm. For the vertically stacked GaSb NW p-FET (LCH of 500 nm), the lowest reported SS of 188 mV/decade and highest ION/IOFF ratio of 3.5 orders were achieved for III-V p-FETs on Si substrate.