Robust low-k film (k=2.1/spl sim/2.5) for 90/65 nm BEOL technology using bilayer film schemes

Abstract

Cu/porous low-k (PLK) with k/spl les/2.5 is the current choice to 65nm and beyond BEOL interconnect technologies. However, critical concerns of the weak physical and chemical structures of PLK (k/spl les/2.5) films on their integration compatibilities, such as CMP defectivity and trench bottom/via smoothness, electrical performances, such as etching/ashing film damaging, and reliability performances, such as electromigration (EM), stress migration (SM) and time-dependent dielectric breakdown (TDDB), still challenge their application feasibility. A novel in-situ formed trench-porous (k=2.5) and via-dense (k=2.7) k=2.5/2.7 bilayer film design was proposed in this study to overcome these facing issues. Cu/PLK DD study results showed that CMP defectivity was /spl sim/4/spl times/ improved and trench bottom was smoothened with a k=2.5/2,7 bilayer PLK approach. Electrical performances using this approach also showed that film damaging from DD etching/ashing was reduced with the higher chemical resistance of the via in the bilayer. Reliability study results demonstrated that an /spl sim/ 2000/spl times/ better DD TDDB lifetime was achieved due to smooth trench bottoms. When changing from Cu/k=2.5 single layer to Cu/k=2.5/2.7 bilayer, SM and EM performances were not impacted. Moreover, with >405 improved hardness and film adhesion the bilayer PLK approach highlights a potential direction to improve Cu/k=2.5 PLK manufacturability in packaging. All these results indicate that this Cu/bilayer BEOL interconnection applicable for 65 nm and beyond generation CMOS technologies.