Design and process technology co-optimization with SADP BEOL in sub-10nm SRAM bitcell

Abstract

Due to the resolution limit of the lithography tools, multiple patterning technologies are being introduced to the back-end of the line (BEOL). For example, LELELE (or LE3, triple litho-etch) or SADP (self-aligned double patterning) [1] are already implemented in 10nm node technology based on a polygon's geometry, its orientation and pitch requirement. However, metal architecture, arrangement of signal and power lines in a metal layer or across metal layers, cause a significant impact on operating performance as well as determine the metal's orientation, which is also an important element for lithographic performance. Therefore, all the factors should be addressed together to arrive at an optimal chip performance.