A Low Power, Transverse Analog FIR Filter as Feed Forward Equalizer in Gigabit Ethernet

Abstract

A low power analog feedforward error equalizer (AFFE) is presented in this paper that cancels precursor inter symbol interferences (ISI) in the front end of gigabit Ethernet on twisted pair interfaces. Forward equalizing in analog domain is beneficial due to consuming lower power and silicon area comparing to digital forward equalizers. Moreover it leads to higher speed which is demanded for real time equalization and also less equalizer complexity. The proposed equalizer is a five tap discrete time filter which is designed in a 0.18mum CMOS technology. The design operates at 125MHz while consuming 42mW from a 1.8V supply. Each filter taps is implemented by an improved Gilbert cell instead of using a multiplier for each bit of the filter tap. Moreover S/H power and speed requirements are relaxed by using redundant S/H's and additional clocking phase