Accelerated fault simulation utilizing multiple-fault propagation

Y. Xing, G. van Brakel, H. Kerkhoff
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引用次数: 1

Abstract

An efficient parallel pattern multiple-fault propagation (MFP) technique for the single stuck-at fault simulation in combinational circuits is presented. This technique is able to operate in conjunction with several existing fault simulation techniques, such as the parallel-pattern simulation and the fanout-free region concept. Experimental results have shown significant improvements in the simulation speed over the existing approaches. The fault simulator described adopts different simulation algorithms at different simulation stages to optimize the simulator performance.<>
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利用多故障传播加速故障模拟
提出了一种有效的并行模式多故障传播(MFP)技术,用于组合电路中单卡滞故障仿真。该技术能够与几种现有的故障模拟技术相结合,例如并行模式模拟和无扇出区域概念。实验结果表明,与现有方法相比,该方法的仿真速度有了显著提高。所描述的故障模拟器在不同的仿真阶段采用不同的仿真算法来优化模拟器的性能。
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Localization and aftereffect of automatic test generation A practical approach for the diagnosis of a MIMD network A complement-based fast algorithm to generate universal test sets for combinational function blocks A control constrained test scheduling approach for VLSI circuits Techniques for reducing hardware requirement of self checking combinational circuits
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