Design for testability in a 200 MFLOPS vector-pipelined processor (VPP)-ULSI

Abstract

The authors describe design for testability (DFT) techniques implemented in a 200 MFLOPS 64-bit floating point vector-pipelined processor (VPP) ULSI. Scan tests were implemented into the central control unit (CCU), as well as into the input/output buffers, which are served by a boundary scan (BS) chain. Newly developed random pattern built-in self tests (BISTs) were implemented into the register file (RF), as well as into two arithmetic units (ADD/SFT and MPY/DIV/LU). Fault coverage for the RF (2-port SRAMs) was 100%. Average fault coverage for pipelined arithmetic units, achieved by a BIST with approximately 1,000,000(2/sup 20/) random patterns, was 98%. Combination of scan test and BIST-internal partial scan-achieves a partial-scan test of the arithmetic units and 99.6% fault coverage for the MPY/DIV/LU.<>