High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors

Abstract

We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body-slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.