Processing impact on the reliability of single metal dual dielectric (SMDD) gate stacks

Abstract

The impact on the reliability of capping layers for low Vt nMOS and pMOS high-k transistors with metal gate is investigated and devices without the resist and strip process are compared to different resist removal recipes. It is found that the interface is not affected by the cap layer, but during the resist removal a thin defect layer is created. While with the cap above the host dielectric the impact of this defect layer is minor, with the cap located below the host the defects are more efficient, increasing the leakage current and reducing the TDDB lifetime.