K. Nii, M. Yabuuchi, Yoshisato Yokoyama, Y. Ishii, T. Okagaki, M. Morimoto, Y. Tsukamoto, Koji Tanaka, Miki Tanaka, S. Tanaka
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引用次数: 7
Abstract
We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.
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