X. Wen, Yoshiyuki Yamashita, S. Kajihara, Laung-Terng Wang, K. Saluja, K. Kinoshita
{"title":"On low-capture-power test generation for scan testing","authors":"X. Wen, Yoshiyuki Yamashita, S. Kajihara, Laung-Terng Wang, K. Saluja, K. Kinoshita","doi":"10.1109/VTS.2005.60","DOIUrl":null,"url":null,"abstract":"Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0's and 1's to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by X-bit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":" September","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"186","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"23rd IEEE VLSI Test Symposium (VTS'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2005.60","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 186
Abstract
Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0's and 1's to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by X-bit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.