W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella, B. Majoux, V. Chowdhury
{"title":"Low current application dedicated process characterization method","authors":"W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella, B. Majoux, V. Chowdhury","doi":"10.1109/ICMTS.2002.1193168","DOIUrl":null,"url":null,"abstract":"We present in this paper a new characterization method dedicated to an analog low consumption application design. A test structure, based on a bandgap reference voltage, that allows parameters extraction at the circuit operating point, is presented. This test structure is used to adjust the final SPICE parameters in order to calibrate the electrical measurement value of each component of the circuit on the chip. An improvement of the design is simulated, tested and validated on silicon.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2002.1193168","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We present in this paper a new characterization method dedicated to an analog low consumption application design. A test structure, based on a bandgap reference voltage, that allows parameters extraction at the circuit operating point, is presented. This test structure is used to adjust the final SPICE parameters in order to calibrate the electrical measurement value of each component of the circuit on the chip. An improvement of the design is simulated, tested and validated on silicon.