CMOS performance benchmarking of Si, InAs, GaAs, and Ge nanowire n- and pMOSFETs with Lg=13 nm based on atomistic quantum transport simulation including strain effects

Abstract

As MOSFET scaling continues [1], new n- and p-channel materials are being actively explored to deliver performance targets better than Si. In this paper, we present CMOS performance benchmarking results for Si, InAs, GaAs, and Ge nanowire (NW) n- and pMOSFETs with LG=13 nm (ITRS node of year 2018 [1-3]) based on atomistic quantum transport simulation [4] and including strain effects [5]. Uniaxial [6] tensile/compressive strain mostly increases nMOS/pMOS drive current and vice versa, but results may be different for low power (LP) operation because strain may also affect the tunneling leakage current. We also discuss the threshold voltage (Vth) sensitivity to strain, which may have an impact on the device variation. Finally, we compare current (I), capacitance (C), and energy (CV2) vs. delay (CV/I) trade-off (for gate or interconnect loading) across different n-channel (Si, InAs, GaAs, Ge) and p-channel (Si, Ge) materials considering extrinsic parasitic components (RSD, Cfringe) for different supply voltages (VDD's). We project that Ge CMOS (using <;110> NWs [7]) with source/drain (S/D) doping density (Nsd) optimized [8] depending on the operating condition (high performance (HP) or LP) may deliver the best drive current and CV2 vs. CV/I while it would also benefit from the homogeneous material integration. For low capacitance (low power consumption), III-V-Ge hybrid CMOS is most advantageous.