Chando Park, J. Kan, C. Ching, Jaesoo Ahn, L. Xue, Rongjun Wang, A. Kontos, S. Liang, M. Bangar, Hao Chen, S. Hassan, M. Gottwald, Xiaochun Zhu, M. Pakala, Seung H. Kang
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引用次数: 39
Abstract
This paper demonstrates the co-optimization of all critical device parameters of perpendicular magnetic tunnel junctions (pMTJ) in 1 Gbit arrays with an equivalent bitcell size of 22 F2 at the 28 nm logic node for embedded STT-MRAM. Through thin-film tuning and advanced etching of sub-50 nm (diameter) pMTJ, high device performance and reliability were achieved simultaneously, including TMR = 150 %, Hc > 1350 Oe, Heff <; 100 Oe, Δ = 85, Ic (35 ns) = 94 μA, Vbreakdown = 1.5 V, and high endurance (> 1012 write cycles). Reliable switching with small temporal variations (<; 5 %) was obtained down to 10 ns. In addition, tunnel barrier integrity and high temperature device characteristics were investigated in order to ensure reliable STT-MRAM operation.
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