Highly Scalable and Reliable Multi-bit/cell Nitride Trapping Nonvolatile Memory Using Enhanced ANS-ONO Process with A Nitridized Interface

Abstract

Multi-bit/cell nitride trapping NVM (Eitan et al., 2000 and 2005) using BTBT-HH erase suffers an "apparent" VT loss due to interface trap (NIT) generation. The array-nitride-sealing (ANS) ONO process (Shih et al., 2005) eliminates this VT loss by blocking hydrogen from the interface. In this work we further outfit the ANS-ONO process with a nitridized Si/SiO2 interface. By introducing a rapid thermal nitridation (RTN) after a low-energy buried diffusion (BD) implantation, the new process provides not only more immunity to HH-induced NIT generation but also a path to scale the BD. A 256Mb testing chip is successfully fabricated by the new approach with excellent natural good yield (>80%) and reliability. Our new process integration shows excellent reliability, scalability, and manufacturability for multi-bit/cell nitride trapping memory