Pub Date : 2018-09-01DOI: 10.1109/diped.2018.8543325
R. Jobava, T. Sato, D. Kaladze
F. G. Bogdanov, L. Svanidze, R. Jobava, MoM Solution to Scattering Problem on MultiRegion Composite Structures with Various Type Material Junctions ...................................... 13 K. Nishimura, M. Kohma, K. Sato, T. Sato, A Beam De-Broadening Algorithm for Atmospheric Radar ................................................................................................................... 19 I. Shamatava, G. Schultz, F. Shubitidze, Accessing UXO Classification Technologies at a Challenging Live-UXO Site ..................................................................................................... 24 I. Petoev, V. Tabatadze, R. Zaridze, S. Invia, Localization of the Scattered Field’s Singularities Using the Method of Auxiliary Sources .............................................................. 28
F. G. Bogdanov, L. Svanidze, R. Jobava，具有不同类型材料结的多区域复合材料结构散射问题的MoM解......................................13 K。Nishimura m . Kohma佐藤k, t .佐藤大气雷达波束De-Broadening算法 ...................................................................................................................19 i Shamatava, g·舒尔茨,f . Shubitidze访问未分类技术在一个具有挑战性的Live-UXO站点 .....................................................................................................24 Petoev,诉Tabatadze r . Zaridze s Invia本地化散射场的奇异性使用辅助源的方法 ..............................................................28
{"title":"Plenary Session","authors":"R. Jobava, T. Sato, D. Kaladze","doi":"10.1109/diped.2018.8543325","DOIUrl":"https://doi.org/10.1109/diped.2018.8543325","url":null,"abstract":"F. G. Bogdanov, L. Svanidze, R. Jobava, MoM Solution to Scattering Problem on MultiRegion Composite Structures with Various Type Material Junctions ...................................... 13 K. Nishimura, M. Kohma, K. Sato, T. Sato, A Beam De-Broadening Algorithm for Atmospheric Radar ................................................................................................................... 19 I. Shamatava, G. Schultz, F. Shubitidze, Accessing UXO Classification Technologies at a Challenging Live-UXO Site ..................................................................................................... 24 I. Petoev, V. Tabatadze, R. Zaridze, S. Invia, Localization of the Scattered Field’s Singularities Using the Method of Auxiliary Sources .............................................................. 28","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132601090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-10DOI: 10.1109/IEDM.2006.346980
D. Temple, C. Bower, D. Malta, J.E. Robinson, P.R. Coffinan, M. Skokan, T. Welch
The paper describes a platform technology for three-dimensional (3-D) integration of multiple layers of silicon integrated circuits. The technology promises to dramatically enhance on-chip signal processing capabilities of a variety of sensor and actuator devices hybridized with Si electronics. Among these applications are high performance infrared focal plane array detectors
{"title":"High Density 3-D Integration Technology for Massively Parallel Signal Processing in Advanced Infrared Focal Plane Array Sensors","authors":"D. Temple, C. Bower, D. Malta, J.E. Robinson, P.R. Coffinan, M. Skokan, T. Welch","doi":"10.1109/IEDM.2006.346980","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346980","url":null,"abstract":"The paper describes a platform technology for three-dimensional (3-D) integration of multiple layers of silicon integrated circuits. The technology promises to dramatically enhance on-chip signal processing capabilities of a variety of sensor and actuator devices hybridized with Si electronics. Among these applications are high performance infrared focal plane array detectors","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134449038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346784
Y. Hayashi
Due to on-going technology paradigm shift from large-integrity LSI to smart LSI with RF/ubiquitous functions, reductions of "parasitic effects" become main concerns to accomplish low-power and high-quality RF operations with the limited interconnect resource. For the power saving, parasitic capacitance of the local interconnects, or the effective dielectric constant (keff), has to be reduced by low-k introduction. For the RF functions, MOSFETs with high fmax, compact-sized passive components such as 3D inductors and high-k MIM capacitors are needed. Structural innovation and novel material introduction are key factors to minimize the "parasitic effects" for the smart integration with RF/ubiquitous functions
{"title":"Structural Evolution in LSI Devices Reducing Parasitic Effects toward RF/ubiquitous Applications","authors":"Y. Hayashi","doi":"10.1109/IEDM.2006.346784","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346784","url":null,"abstract":"Due to on-going technology paradigm shift from large-integrity LSI to smart LSI with RF/ubiquitous functions, reductions of \"parasitic effects\" become main concerns to accomplish low-power and high-quality RF operations with the limited interconnect resource. For the power saving, parasitic capacitance of the local interconnects, or the effective dielectric constant (keff), has to be reduced by low-k introduction. For the RF functions, MOSFETs with high fmax, compact-sized passive components such as 3D inductors and high-k MIM capacitors are needed. Structural innovation and novel material introduction are key factors to minimize the \"parasitic effects\" for the smart integration with RF/ubiquitous functions","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115436147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346787
M. Zimmermann, J. Burghartz, W. Appel, N. Remmers, C. Burwick, R. Wurz, O. Tobail, M. Schubert, G. Palfinger, J. Werner
Various new applications of silicon technology, such as 3D circuit integration (Patti, 2006), system-on-chip (SoC), system-in-package (SiP), and electronics on foil or textile (Sanda et al.,2005), call for low-cost manufacturing and assembly of ultra-thin chips (5-50 mum). Practically all currently pursued concepts for fabricating thin chips are based on post-process thinning at wafer level, which, at thickness <50 mum, require application of a costly handle substrate. Also, grinding techniques applied to very thin wafers may lead to defect formation, thickness non-uniformity (wedging), and wafer fracture, thus causing yield loss and leading to high cost at this late stage of manufacture (Feil et al., 204). The paper proposed a new concept based on thin-chip fabrication by wafer pre-processing prior to the CMOS integration instead of post-process thinning of the entire wafer. There, the conventional chip dicing is replaced by a novel Pick, Crack & Placetrade process, through which the thin chip fabrication and assembly processes are seamlessly connected
{"title":"A Seamless Ultra-Thin Chip Fabrication and Assembly Process","authors":"M. Zimmermann, J. Burghartz, W. Appel, N. Remmers, C. Burwick, R. Wurz, O. Tobail, M. Schubert, G. Palfinger, J. Werner","doi":"10.1109/IEDM.2006.346787","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346787","url":null,"abstract":"Various new applications of silicon technology, such as 3D circuit integration (Patti, 2006), system-on-chip (SoC), system-in-package (SiP), and electronics on foil or textile (Sanda et al.,2005), call for low-cost manufacturing and assembly of ultra-thin chips (5-50 mum). Practically all currently pursued concepts for fabricating thin chips are based on post-process thinning at wafer level, which, at thickness <50 mum, require application of a costly handle substrate. Also, grinding techniques applied to very thin wafers may lead to defect formation, thickness non-uniformity (wedging), and wafer fracture, thus causing yield loss and leading to high cost at this late stage of manufacture (Feil et al., 204). The paper proposed a new concept based on thin-chip fabrication by wafer pre-processing prior to the CMOS integration instead of post-process thinning of the entire wafer. There, the conventional chip dicing is replaced by a novel Pick, Crack & Placetrade process, through which the thin chip fabrication and assembly processes are seamlessly connected","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115473838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346960
H. Wang, Shih-Hian Huang, Ching-Wei Tsai, Hsien-Hsin Lin, Tze-Liang Lee, Shih-Chang Chen, C. H. Diaz, M. Liang, J. Sun
A study was performed to investigate the effect of multiple stressors on CMOS devices on (110) and (100) substrates with different channel directions. For the first time, 87% ION-IOFF improvement is achieved by utilizing SiGe-S/D and compressive contact etch stop layer (c-CESL) for PMOS devices on (110) substrate with lang111'rang channel direction. The improvement is similar to that on conventional (100) substrate with lang110>rangchannel direction and can be explained by piezoresistive coefficients. Record PMOS device performance of Ion = 900 muA/mum at Ioff = 100 nA/mum and VDD = 1.0V for 40nm gate length is demonstrated
{"title":"High-Performance PMOS Devices on (110)/<111'> Substrate/Channel with Multiple Stressors","authors":"H. Wang, Shih-Hian Huang, Ching-Wei Tsai, Hsien-Hsin Lin, Tze-Liang Lee, Shih-Chang Chen, C. H. Diaz, M. Liang, J. Sun","doi":"10.1109/IEDM.2006.346960","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346960","url":null,"abstract":"A study was performed to investigate the effect of multiple stressors on CMOS devices on (110) and (100) substrates with different channel directions. For the first time, 87% ION-IOFF improvement is achieved by utilizing SiGe-S/D and compressive contact etch stop layer (c-CESL) for PMOS devices on (110) substrate with lang111'rang channel direction. The improvement is similar to that on conventional (100) substrate with lang110>rangchannel direction and can be explained by piezoresistive coefficients. Record PMOS device performance of Ion = 900 muA/mum at Ioff = 100 nA/mum and VDD = 1.0V for 40nm gate length is demonstrated","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"130 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124244541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346819
R. Gusmeroli, C. M. Compagnoni, A. Riva, A. Spinelli, A. Lacaita, M. Bonanomi, A. Visconti
We investigate the properties of traps in the SiO2 by means of a statistical analysis of random telegraph noise in Flash memory arrays. We develop a new physical model for the statistical superposition of the elementary Markov processes describing traps occupancy, able to explain the experimental evidence for cell threshold voltage instability. Comparing modeling results with experimental data allowed the estimation of the energy and space distribution of oxide defects
{"title":"Defects spectroscopy in SiO2 by statistical random telegraph noise analysis","authors":"R. Gusmeroli, C. M. Compagnoni, A. Riva, A. Spinelli, A. Lacaita, M. Bonanomi, A. Visconti","doi":"10.1109/IEDM.2006.346819","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346819","url":null,"abstract":"We investigate the properties of traps in the SiO2 by means of a statistical analysis of random telegraph noise in Flash memory arrays. We develop a new physical model for the statistical superposition of the elementary Markov processes describing traps occupancy, able to explain the experimental evidence for cell threshold voltage instability. Comparing modeling results with experimental data allowed the estimation of the energy and space distribution of oxide defects","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127279100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346938
T. Krishnamohan, C. Jungemann, Donghyun Kim, E. Ungersboeck, S. Selberherr, P. Wong, Y. Nishi, K. Saraswat
Using the non-local empirical pseudopotential method (bandstructure), full-band Monte-Carlo simulations (transport), 1D Poisson-Schrodinger (electrostatics) and detailed band-to-band-tunneling (BTBT) (including bandstructure and quantum effects) simulations, the effect of uniaxial- and biaxial-strain, band-structure, mobility, effective masses, density of states, channel orientation and high-field transport on the drive current, off-state leakage and switching delay in nano-scale, Si, SiGe and Ge, p-MOS DGFETs is thoroughly and systematically investigated
{"title":"Theoretical Investigation Of Performance In Uniaxially- and Biaxially-Strained Si, SiGe and Ge Double-Gate p-MOSFETs","authors":"T. Krishnamohan, C. Jungemann, Donghyun Kim, E. Ungersboeck, S. Selberherr, P. Wong, Y. Nishi, K. Saraswat","doi":"10.1109/IEDM.2006.346938","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346938","url":null,"abstract":"Using the non-local empirical pseudopotential method (bandstructure), full-band Monte-Carlo simulations (transport), 1D Poisson-Schrodinger (electrostatics) and detailed band-to-band-tunneling (BTBT) (including bandstructure and quantum effects) simulations, the effect of uniaxial- and biaxial-strain, band-structure, mobility, effective masses, density of states, channel orientation and high-field transport on the drive current, off-state leakage and switching delay in nano-scale, Si, SiGe and Ge, p-MOS DGFETs is thoroughly and systematically investigated","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125066724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346827
H. Johari, F. Ayazi
This paper introduces the capacitive bulk acoustic wave (BAW) silicon disk gyroscope. The capacitive BAW disk gyroscopes operate in the frequency range of 2-8MHz, are stationary devices with vibration amplitudes less than 20nm, and achieve very high quality factors (Q) in low vacuum (and even in atmosphere), which simplifies their wafer-scale packaging. The device has lower operating voltages compared to low-frequency gyroscopes, which simplifies the interface circuit design and implementation in standard CMOS
{"title":"Capacitive Bulk Acoustic Wave Silicon Disk Gyroscopes","authors":"H. Johari, F. Ayazi","doi":"10.1109/IEDM.2006.346827","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346827","url":null,"abstract":"This paper introduces the capacitive bulk acoustic wave (BAW) silicon disk gyroscope. The capacitive BAW disk gyroscopes operate in the frequency range of 2-8MHz, are stationary devices with vibration amplitudes less than 20nm, and achieve very high quality factors (Q) in low vacuum (and even in atmosphere), which simplifies their wafer-scale packaging. The device has lower operating voltages compared to low-frequency gyroscopes, which simplifies the interface circuit design and implementation in standard CMOS","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122574401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346984
T. Sugizaki, M. Nakamura, M. Yanagita, M. Honda, M. Shinohara, T. Ikuta, T. Ohchi, K. Kugimiya, R. Yamamoto, S. Kanda, I. Yamamura, K. Yagami, T. Oda
We developed novel SRAM cells using bulk thyristor-RAM (BT-RAM). BT-RAM, formed on bulk Si wafers, is low cost and has good compatibility with logic process flows. BT-RAM has excellent performance, with a 100-ps read/write, high Ion/Ioff current ratio (> 108), and low standby current (< 0.5 nA/cell). We can expect the ideal cell size to be as low as 30 F2, one-fourth that of a conventional 6T-SRAM cell, by using selective epitaxy technique for anode regions (SEA). BT-RAM provides us with solutions to many inherent problems in 6T-SRAM in the 65-nm generation and beyond
{"title":"Ultra High-speed Novel Bulk Thyristor-SRAM (BT-RAM) Cell with Selective Epitaxy Anode (SEA)","authors":"T. Sugizaki, M. Nakamura, M. Yanagita, M. Honda, M. Shinohara, T. Ikuta, T. Ohchi, K. Kugimiya, R. Yamamoto, S. Kanda, I. Yamamura, K. Yagami, T. Oda","doi":"10.1109/IEDM.2006.346984","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346984","url":null,"abstract":"We developed novel SRAM cells using bulk thyristor-RAM (BT-RAM). BT-RAM, formed on bulk Si wafers, is low cost and has good compatibility with logic process flows. BT-RAM has excellent performance, with a 100-ps read/write, high Ion/Ioff current ratio (> 108), and low standby current (< 0.5 nA/cell). We can expect the ideal cell size to be as low as 30 F2, one-fourth that of a conventional 6T-SRAM cell, by using selective epitaxy technique for anode regions (SEA). BT-RAM provides us with solutions to many inherent problems in 6T-SRAM in the 65-nm generation and beyond","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114298032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346918
G. Buh, G. Yon, T. Park, Jin-Wook Lee, Jihyun Kim, Y. Wang, Lucia Feng, Xiaoru Wang, Y. Shin, Siyoung Choi, U. Chung, J. Moon, B. Ryu
We report on the integration of sub-melt laser spike annealing (LSA) on W-gate stacked DRAM. We applied the LSA as a reactivation in back-end processes to comply with the considerable metal-pattern effects and strong DRAM thermal-budget. Improvements in drive currents of peripheral transistors (4 %/14 % for n/p-FETs) are achieved by using the LSA without incurring short channel effect (SCE) while minimizing pattern effects of metal gate. DRAM cell transistors also show improvements in drive current, junction leakage, and GIDL (gate-induced drain leakage) without laser-induced local defects and reliability degradation
{"title":"Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub 50 nm Node DRAM","authors":"G. Buh, G. Yon, T. Park, Jin-Wook Lee, Jihyun Kim, Y. Wang, Lucia Feng, Xiaoru Wang, Y. Shin, Siyoung Choi, U. Chung, J. Moon, B. Ryu","doi":"10.1109/IEDM.2006.346918","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346918","url":null,"abstract":"We report on the integration of sub-melt laser spike annealing (LSA) on W-gate stacked DRAM. We applied the LSA as a reactivation in back-end processes to comply with the considerable metal-pattern effects and strong DRAM thermal-budget. Improvements in drive currents of peripheral transistors (4 %/14 % for n/p-FETs) are achieved by using the LSA without incurring short channel effect (SCE) while minimizing pattern effects of metal gate. DRAM cell transistors also show improvements in drive current, junction leakage, and GIDL (gate-induced drain leakage) without laser-induced local defects and reliability degradation","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122179932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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