W. Taylor, C. Capasso, B. Min, B. Winstead, E. Verret, K. Loiko, D. Gilmer, R. Hegde, J. Schaeffer, E. Luckowski, A. Martínez, M. Raymond, C. Happ, D. Triyoso, S. Kalpat, A. Haggag, D. Roan, J. Nguyen, L. La, L. Hebert, J. Smith, D. Jovanovic, D. Burnett, M. Foisy, N. Cave, P. Tobin, S. Samavedam, S. B. White, S. Venkatesan
{"title":"Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS","authors":"W. Taylor, C. Capasso, B. Min, B. Winstead, E. Verret, K. Loiko, D. Gilmer, R. Hegde, J. Schaeffer, E. Luckowski, A. Martínez, M. Raymond, C. Happ, D. Triyoso, S. Kalpat, A. Haggag, D. Roan, J. Nguyen, L. La, L. Hebert, J. Smith, D. Jovanovic, D. Burnett, M. Foisy, N. Cave, P. Tobin, S. Samavedam, S. B. White, S. Venkatesan","doi":"10.1109/IEDM.2006.346861","DOIUrl":null,"url":null,"abstract":"We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) CMOS technology. Inversion Tox (Tinv) values of 16Aring/18Aring (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm 2 and enable self-heated drive currents of 850/325muA/mum at 1nA/mum off-state leakage and Vdd=1V (900/340muA/mum non-self-heated). Additionally, the NMOS drive current of 1550 muA/mum (1650muA/mum non-self-heated) at an Ioff = 100nA/mum and Vdd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2006.346861","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) CMOS technology. Inversion Tox (Tinv) values of 16Aring/18Aring (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm 2 and enable self-heated drive currents of 850/325muA/mum at 1nA/mum off-state leakage and Vdd=1V (900/340muA/mum non-self-heated). Additionally, the NMOS drive current of 1550 muA/mum (1650muA/mum non-self-heated) at an Ioff = 100nA/mum and Vdd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
